This thesis presents a study on implementing a low-density parity-check (LDPC) decoder on a graphics processing unit (GPU) for 5G New Radio (NR). The proposed modifications include distributed execution configuration, compressed parity-check matrices (PCM) and message passing matrices to save memory space and applying the optimal iteration limit to the decoder. The performance of the LDPC decoder is evaluated using various testing cases with different algorithms, code rates and transport block sizes. The results show that the proposed decoder has more than 5× decoding speedup improvement on the short codes and more than 20× decoding speedup improvement on the long codes, while maintaining the error-correction performance. The optimal iteration limit is found to depend on the specific code rate and transport block size. The layered scheduling is a viable option on short codes over noisy channels.
This thesis presents a study on implementing a low-density parity-check (LDPC) decoder on a graphics processing unit (GPU) for 5G New Radio (NR). The proposed modifications include distributed execution configuration, compressed parity-check matrices (PCM) and message passing matrices to save memory space and applying the optimal iteration limit to the decoder. The performance of the LDPC decoder is evaluated using various testing cases with different algorithms, code rates and transport block sizes. The results show that the proposed decoder has more than 5× decoding speedup improvement on the short codes and more than 20× decoding speedup improvement on the long codes, while maintaining the error-correction performance. The optimal iteration limit is found to depend on the specific code rate and transport block size. The layered scheduling is a viable option on short codes over noisy channels.
This thesis investigates the acceleration of Low-Density Parity-Check (LDPC) decoding for 5G New Radio (5G NR) communication systems using NVIDIA Graphics Processing Units (GPUs) and the NVIDIA Sionna simulation framework. LDPC codes are widely used in modern wireless communication systems, including 5G NR, because of their strong error-correction capabilities. However, the decoding process is computationally intensive since it relies on iterative algorithms that require multiple rounds of calculations before a final decoding decision can be made. As communication systems continue to demand higher data rates and lower latency, improving the efficiency of LDPC decoding has become increasingly important. A complete LDPC-based communication system was implemented using Sionna. The system included Cyclic Redundancy Check (CRC) encoding, LDPC encoding, modulation, transmission through an Additive White Gaussian Noise (AWGN) channel, demodulation, LDPC decoding, and CRC decoding. Three LDPC decoding algorithms were evaluated: Sum-Product Algorithm (SPA), Min-Sum Algorithm (MSA), and Offset Min-Sum Algorithm (OMSA). The study focused on measuring decoding performance on NVIDIA GPUs and investigating optimization techniques that could reduce LDPC decoding execution time while maintaining reliable decoding performance. Two optimization techniques were implemented and evaluated: CRC-based early termination and Accelerated Linear Algebra (XLA) graph compilation. Early termination allowed the LDPC decoder to stop before reaching the maximum number of decoding iterations. XLA was used to improve the efficiency of the computations executed during LDPC decoding. The performance of the optimized implementations was compared with a baseline implementation across different signal-to-noise ratio (SNR) values. The results showed that both optimization techniques reduced decoding execution time, while maintaining reliable Block Error Rate (BLER) performance compared to the baseline scheme.
Low-Density Parity-Check (LDPC) codes are linear error-correcting codes used to establish reliable communication between units on a noisy transmission channel in mobile telecommunications. LDPC algorithms detect and recover altered or corrupted message bits using sparse parity-check matrices in order to decipher messages correctly. LDPC codes have been shown to be fitting coding schemes for the fifth generation (5G) New Radio (NR), according to the third generation partnership project (3GPP). TietoEvry, a consultant in telecom, has discovered that optimizations of LDPC decoding algorithms can be achieved/obtained with the use of a parallel computing platform called Compute Unified Device Architecture (CUDA), developed by NVIDIA. This platform utilizes the capabilities of a graphics processing unit (GPU) rather than a central processing unit (CPU), which in turn provides parallel computing. An optimized version of an LDPC decoding algorithm, the Min-Sum Algorithm (MSA), is implemented in CUDA and in C++ for comparison in terms of CPU execution time, to explore the capabilities that CUDA offers. The testing is done with a set of 12 sparse parity-check matrices and input-channel messages with different sizes. As a result, the CUDA implementation executes approximately 55% faster than a standard, unoptimized C++ implementation.
Modern 5G New Radio (NR) systems demand high data rates, low delays, and consistent reliability, particularly in Cloud-Based Radio Access Network (C-RAN) where standard hardware handles signal processing. To meet these requirements, 5G NR uses Low-Density Parity-Check (LDPC) codes for channel coding. Although LDPC codes provide robust error correction, decoding them is computationally intensive. Consequently, achieving efficient LDPC software decoding is a significant obstacle in creating high-performing and adaptable 5G systems. Previous research has shown that performing Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoding in parallel on Graphics Processing Units (GPUs) using proprietary tools like CUDA can yield much higher performance than sequential Central Processing Unit (CPU) approaches. However, relying on such solutions can result in vendor lock-in and reduce portability across hardware platforms. This thesis investigates whether SYCL, a hardware-agnostic parallel programming framework based on C++, can provide efficient QC-LDPC decoding suitable for 5G NR C-RAN environments. This work introduces a QC-LDPC decoder implemented in SYCL that utilizes the Layered Offset Min-Sum algorithm. Its performance is evaluated against a comparable sequential C++ version and a CUDA-based GPU implementation. The experiments employ simulated 5G NR data, varying message sizes, base graph configurations, and channel conditions. The findings indicate that SYCL enables the code to operate on both CPUs and GPUs, though its effectiveness depends on the underlying hardware and specific workloads. On CPUs, SYCL does not surpass the sequential approach due to additional runtime overhead. On GPUs, SYCL shows advantages in the most computationally intensive decoding scenarios but still lags behind native CUDA implementations. These out comes highlight key trade-offs among performance, portability, and reliance on specific vendors when selecting programming models for QC-LDPC decoding in 5G systems.
Over the last ten years, there has been an incremental growth of mobile network data traffic. The evolution leading to the development of 5G stands as a testament to the increased demands for high speed networks. Channel coding plays a pivotal role in 5G networks, making it possible to recover messages from errors introduced when sent through the network. Channel decoding is however a time consuming task for a receiver, and making optimization to this process could therefore have a significant impact on receiver processing time. Low-Density Parity-Check (LDPC) codes are one of the channel coding schemes used in the 5G standard. These codes could benefit from parallel processing, making Graphics Processing Units (GPUs) with their parallel computation abilities a possible platform for effective LDPC decoding. In this thesis, our goal is to evaluate a GPU as a platform for 5G LDPC decoding. The LDPC codes adhering to the 5G standard belong to the Quasi-Cyclic LDPC (QC-LDPC) subclass. Optimizations targeting this subclass, as well as other optimization techniques, are implemented in our thesis project to promote fast execution times. A GPU-based decoder is evaluated against a Central Processing Unit (CPU)-based decoder, written with Compute Unified Device Architecture (CUDA) and C++ respectively. The functionally equivalent decoders implement the layered offset Min-Sum Algorithm (MSA) with early termination to decode messages. Execution time for the decoders were measured while varying message size, Signal-to-Noise Ratio (SNR) and maximum iterations. Additionaly, we evaluated the decoders with and without including early termination, and also evaluated the GPU-decoder when it was integrated into a MATLAB 5G channel simulator used by Tietoevry. The results from the experiments showed that the GPU-based decoder experienced up to 4.3 times faster execution than the CPU-based decoder for message sizes ranging from 3000-12000 bits. The GPU-based decoder however experienced a higher baseline execution time, making the CPU-based decoder faster for smaller message sizes. It was also concluded that the benefit of including early termination in the decoder generally outweighs the cost of additional processing time.
In this work, iterative decoders for Low-Density Parity-Check (LDPC) codes are analyzed and optimized for low computational complexity. LDPC block codes are now widely used in industry standards such as Wi-Fi or 5G New Radio (NR). Hence, there is a strong need for decoder concepts suitable for hardware designs. In addition, terminated LDPC convolutional codes are promising candidates for next-generation communication systems. The main theme of this work is to investigate low-overhead strategies for reducing the computational complexity of iterative decoders. Two aspects are considered for fast decoding of the LDPC block codes in 5G NR. Firstly, an efficient but simple-to determine update schedule for the iterative decoding process, i.e., the sequence of updates on different parts of a codeword, is proposed. Secondly, Early Termination (ET), i.e., an option to stop decoding before a maximal number of iterations is exhausted, is improved in two ways: On the one hand, a partial evaluation of the code’s Parity-Check (PC) equations speeds up the detection of valid codewords. On the other hand, a novel criterion detects when the decoding process is unlikely to converge and stops the decoding before a lot of resources are wasted on futile iterations. The combination of all techniques results in a decoder with significant reduction of the computational complexity compared to a decoder without these methods. Still, only few additional residual decoding errors are produced. This work also contains an analysis of various aspects of a Windowed Decoder (WD), which is a specialized decoder design for LDPC convolutional codes. A WD can be configured in even more ways than a decoder for block codes. The analysis in this work assumes a normalization of the computational complexity to a certain maximal value. With this setup, it is shown that a larger size of the decoding window may be preferable over a smaller size to minimize the computational complexity. Furthermore, various window update strategies (determining in which way the code symbol reliabilities are updated in each window) and variations of ET are compared to identify a well-suited WD configuration. Lastly, strategies with Dynamic Scheduling (DS) are considered to further reduce the computational complexity. A novel fixed approach derived from several DS strategies performs well without actual dynamic knowledge of the decoder state. All in all, the optimized WD configuration halves the computational complexity of a block decoder while maintaining an acceptable loss in the decoding performance measured by the number of residual decoding errors. A comparison of systems with Hybrid Automatic Repeat reQuest (HARQ) expands the scope of this work into the domain of error control by retransmissions. The analyzed systems make use of the decoder output, e.g., the final code-symbol reliabilities, to assemble dynamic retransmissions that are as short as possible and contain specifically selected code symbols. These systems stand in contrast to contemporary implementations of HARQ that only use imprecise feedback messages. Still, some compatibility with existing systems is achieved by assuming a limited feedback channel, which requires clever compression of the feedback information. A novel HARQ system is proposed, which evaluates the code’s PC equations to avoid the computational overhead of soft-value processing. The throughput with the proposed system is found to be improved compared to a reference system that evaluates code-symbol reliabilities. Finally, approximations of the accurate message-update rules of the Sum–Product Algorithm (SPA) are analyzed. With fixed-point arithmetic, Look-Up Tables (LUTs) are a promising approach to approximate functions that are costly to compute. It is shown that an optimized LUT with just nine entries can be used in a fixed-point decoder such that the decoding performance is close to that of a floating-point decoder with accurate message updates.
Abstract In order to cater to the needs of the 5G standard, one of the prominent solutions in terms of high coding gain, high throughput and low power dissipation is the 5G NR LDPC (New Radio Low Density Parity Check) codes which have been adopted by 5G Standard. LDPC codes are the successful Third Generation Forward Error Correcting codes. An Efficient decoder is the key to the success of any Error Correcting Code. LDPC codes are one whose parity check matrix have a very few non zero entries. 5G NR LDPC codes are constructed by Protographs or base graphs and are block structured. This paper improves the performance of Layered Iterative minsum Approximation Message Passing decoding Algorithm using Rate Matching, Fixed Point Quantization and Offset minsum techniques. Rate Matching is to maintain the exact number of encoded blocks with in the TTI. Simulation of this algorithm with BPSK encoding over AWGN channel shows that BER of 10-3 gives Eb/No of~2 dB for the block length of 105.