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Decoder Improvements for Fast Decoding of Low-Density Parity-Check Codes

Janik Frenzel

Published Jan 1, 2020• 0 citations
OpenAlex

Abstract

In this work, iterative decoders for Low-Density Parity-Check (LDPC) codes are analyzed and optimized for low computational complexity. LDPC block codes are now widely used in industry standards such as Wi-Fi or 5G New Radio (NR). Hence, there is a strong need for decoder concepts suitable for hardware designs. In addition, terminated LDPC convolutional codes are promising candidates for next-generation communication systems. The main theme of this work is to investigate low-overhead strategies for reducing the computational complexity of iterative decoders. Two aspects are considered for fast decoding of the LDPC block codes in 5G NR. Firstly, an efficient but simple-to determine update schedule for the iterative decoding process, i.e., the sequence of updates on different parts of a codeword, is proposed. Secondly, Early Termination (ET), i.e., an option to stop decoding before a maximal number of iterations is exhausted, is improved in two ways: On the one hand, a partial evaluation of the code’s Parity-Check (PC) equations speeds up the detection of valid codewords. On the other hand, a novel criterion detects when the decoding process is unlikely to converge and stops the decoding before a lot of resources are wasted on futile iterations. The combination of all techniques results in a decoder with significant reduction of the computational complexity compared to a decoder without these methods. Still, only few additional residual decoding errors are produced. This work also contains an analysis of various aspects of a Windowed Decoder (WD), which is a specialized decoder design for LDPC convolutional codes. A WD can be configured in even more ways than a decoder for block codes. The analysis in this work assumes a normalization of the computational complexity to a certain maximal value. With this setup, it is shown that a larger size of the decoding window may be preferable over a smaller size to minimize the computational complexity. Furthermore, various window update strategies (determining in which way the code symbol reliabilities are updated in each window) and variations of ET are compared to identify a well-suited WD configuration. Lastly, strategies with Dynamic Scheduling (DS) are considered to further reduce the computational complexity. A novel fixed approach derived from several DS strategies performs well without actual dynamic knowledge of the decoder state. All in all, the optimized WD configuration halves the computational complexity of a block decoder while maintaining an acceptable loss in the decoding performance measured by the number of residual decoding errors. A comparison of systems with Hybrid Automatic Repeat reQuest (HARQ) expands the scope of this work into the domain of error control by retransmissions. The analyzed systems make use of the decoder output, e.g., the final code-symbol reliabilities, to assemble dynamic retransmissions that are as short as possible and contain specifically selected code symbols. These systems stand in contrast to contemporary implementations of HARQ that only use imprecise feedback messages. Still, some compatibility with existing systems is achieved by assuming a limited feedback channel, which requires clever compression of the feedback information. A novel HARQ system is proposed, which evaluates the code’s PC equations to avoid the computational overhead of soft-value processing. The throughput with the proposed system is found to be improved compared to a reference system that evaluates code-symbol reliabilities. Finally, approximations of the accurate message-update rules of the Sum–Product Algorithm (SPA) are analyzed. With fixed-point arithmetic, Look-Up Tables (LUTs) are a promising approach to approximate functions that are costly to compute. It is shown that an optimized LUT with just nine entries can be used in a fixed-point decoder such that the decoding performance is close to that of a floating-point decoder with accurate message updates.

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The development of the Fifth Generation (5G) New Radio (NR) provides several significant advantages when compared to the fourth generation (4G) Long Term Evolution (LTE) in mobile communications. Due to the outstanding characteristics of Low-Density Parity-Check (LDPC) codes such as high decoding performance, high throughput, low complexity, they have been accepted as the standard codes for the 5G NR. In this paper, we propose two LDPC decoding algorithms: Hybrid Offset Min-Sum (HOMS) and Variable Offset Min-Sum (VOMS), which are aimed at improving the error correction performance. The main idea of the HOMS/VOMS algorithm is to apply modified factors to both variable-nodes and check-nodes updated processing in order to compensate the extrinsic messages overestimation of the MS-based algorithms and increase the protection ability for degree-1 variable-nodes. The simulation results show that at the Bit-Error-Rate (BER) of 10-5, the proposed HOMS/VOMS algorithm achieves the decoding gain up to 0.2 dB compared to the Offset Min-Sum (OMS) algorithm, with a slight increase in decoding complexity.

Journal of Communications•Jan 1, 2022•3 citations
In this work, iterative decoders for Low-Density Parity-Check (LDPC) codes are analyzed and optimized for low computational complexity. LDPC block codes are now widely used in industry standards such as Wi-Fi or 5G New Radio (NR). Hence, there is a strong need for decoder concepts suitable for hardware designs. In addition, terminated LDPC convolutional codes are promising candidates for next-generation communication systems. The main theme of this work is to investigate low-overhead strategies for reducing the computational complexity of iterative decoders. Two aspects are considered for fast decoding of the LDPC block codes in 5G NR. Firstly, an efficient but simple-to determine update schedule for the iterative decoding process, i.e., the sequence of updates on different parts of a codeword, is proposed. Secondly, Early Termination (ET), i.e., an option to stop decoding before a maximal number of iterations is exhausted, is improved in two ways: On the one hand, a partial evaluation of the code’s Parity-Check (PC) equations speeds up the detection of valid codewords. On the other hand, a novel criterion detects when the decoding process is unlikely to converge and stops the decoding before a lot of resources are wasted on futile iterations. The combination of all techniques results in a decoder with significant reduction of the computational complexity compared to a decoder without these methods. Still, only few additional residual decoding errors are produced. This work also contains an analysis of various aspects of a Windowed Decoder (WD), which is a specialized decoder design for LDPC convolutional codes. A WD can be configured in even more ways than a decoder for block codes. The analysis in this work assumes a normalization of the computational complexity to a certain maximal value. With this setup, it is shown that a larger size of the decoding window may be preferable over a smaller size to minimize the computational complexity. Furthermore, various window update strategies (determining in which way the code symbol reliabilities are updated in each window) and variations of ET are compared to identify a well-suited WD configuration. Lastly, strategies with Dynamic Scheduling (DS) are considered to further reduce the computational complexity. A novel fixed approach derived from several DS strategies performs well without actual dynamic knowledge of the decoder state. All in all, the optimized WD configuration halves the computational complexity of a block decoder while maintaining an acceptable loss in the decoding performance measured by the number of residual decoding errors. A comparison of systems with Hybrid Automatic Repeat reQuest (HARQ) expands the scope of this work into the domain of error control by retransmissions. The analyzed systems make use of the decoder output, e.g., the final code-symbol reliabilities, to assemble dynamic retransmissions that are as short as possible and contain specifically selected code symbols. These systems stand in contrast to contemporary implementations of HARQ that only use imprecise feedback messages. Still, some compatibility with existing systems is achieved by assuming a limited feedback channel, which requires clever compression of the feedback information. A novel HARQ system is proposed, which evaluates the code’s PC equations to avoid the computational overhead of soft-value processing. The throughput with the proposed system is found to be improved compared to a reference system that evaluates code-symbol reliabilities. Finally, approximations of the accurate message-update rules of the Sum–Product Algorithm (SPA) are analyzed. With fixed-point arithmetic, Look-Up Tables (LUTs) are a promising approach to approximate functions that are costly to compute. It is shown that an optimized LUT with just nine entries can be used in a fixed-point decoder such that the decoding performance is close to that of a floating-point decoder with accurate message updates.
5G technology new radios (5G NR) require high-speed decoders that operate on highly irregular low-density parity-check (LDPC) codes.LDPC decoders have gained significant attention due to their excellent error correction performance.This study evaluates on different algorithms and scheduling techniques used for LDPC decoders.The analysis highlights that Min-Sum-based approaches can reduce the computational complexity compared to the basic sum-product algorithm, while the normalized and extended Min-Sum algorithms provide a better trade-off owing to their accurate value assumptions.Furthermore, different scheduling methods are implied for MS to improve speed and reduce latency.This study provides a comparative analysis of the algorithms and architectures that yield high throughputs without compromising performance efficiency.The LNMS algorithm with a data-level rescheduling technique resolves data dependency issues.This resolves the complexity of CN and VN and improves the throughput, making it suitable for 5G NR applications.The decoded throughput achieved with this scheduling is 7.0 Gbps.This throughput is achieved by maintaining the standard parameters and worst case parameters, such as four/eight iterations, BG1, and a code rate of 0.8/0.5.The evaluated architectures are implemented on Field Programmable Gate Array (FPGA) devices.This study aids in selecting the optimal architecture and scheduling techniques for LDPC decoders by considering various performance standards to deploy wireless networks in 5G and beyond.
Nonbiliary low-density parity-check (LDPC) codes can lead to excellent error performance while the codewords are of short or moderate length. However, the high decoding complexity of nonbiliary LDPC codes inevitably depreciates their practical values. The computational bottleneck arises from the check node processing in the iterative message passing (MP) algorithms which terminate when either all parity checks are satisfied or the maximum iteration number is reached. We have observed that for undecodable blocks, the MP algorithms always run up to the maximum iteration limit and therefore cannot generate the correct codeword. Thus, it would be better to terminate the algorithms early so as to save the unnecessary computational time and reduce the extra power consumption when undecodable blocks are experienced. In this paper, we propose a new T-tolerance stopping criterion for LDPC decoders by exploiting the fact that the total a posteriori probability (APP) should increase as the iteration number grows. Simulation results demonstrate that our proposed new T-tolerance criterion can greatly reduce the average iteration number (complexity) while restricting the decoding performance degradation within 0.1 dB in low bit-energy-to-noise ratio scenarios.
Low-density parity-check (LDPC) codes offer excellent performance at competitive levels of complexity. Short block length LDPC codes avoid the large processing latency incurred by the large block lengths classically considered for this class of codes, making them a potential candidate for next generation wireless communications systems. In this paper, a novel informed dynamic scheduling (IDS) approach for decoding LDPC codes is developed based on the use of the current message reliabilities and the residuals of the potential updates to select the messages passed in the graph during iterative Sum Product decoding. An alternative measure of the iteration of the IDS schemes is also proposed which highlights the high cost of those algorithms in terms of processing complexity and motivates the development of the proposed approach. The proposed Rel.-RBP decoding algorithm offers very fast convergence at reduced complexity and gains in error rate performance when compared to the previous schemes.
This thesis presents a study on implementing a low-density parity-check (LDPC) decoder on a graphics processing unit (GPU) for 5G New Radio (NR). The proposed modifications include distributed execution configuration, compressed parity-check matrices (PCM) and message passing matrices to save memory space and applying the optimal iteration limit to the decoder. The performance of the LDPC decoder is evaluated using various testing cases with different algorithms, code rates and transport block sizes. The results show that the proposed decoder has more than 5× decoding speedup improvement on the short codes and more than 20× decoding speedup improvement on the long codes, while maintaining the error-correction performance. The optimal iteration limit is found to depend on the specific code rate and transport block size. The layered scheduling is a viable option on short codes over noisy channels.
The expanding demand for high-speed communications has resulted in development of high-throughput error-correcting techniques required by emerging communication standards. Low-Density Parity-Check (LDPC) codes are a class of linear block codes that achieve near-capacity performance and have been selected as part of many digital communication standards. Stochastic computation has been proposed as a hardware efficient approach for decoding LDPC codes. Using stochastic computation, all messages in the iterative decoding process are represented by Bernoulli sequences. Computations on these sequences are performed bit-by-bit using simple logic operations. Furthermore, serial messages used in stochastic decoders help alleviate routing congestion in hardware implementation of decoder. These factors make stochastic decoding a low complexity alternative to implement LDPC decoders. In this dissertation, we analyze the characteristics of stochastic decoding and propose reduced-latency designs for stochastic LDPC decoders to achieve improved performance on various channel models.
The development of the Fifth Generation (5G) New Radio (NR) provides several significant advantages when compared to the fourth generation (4G) Long Term Evolution (LTE) in mobile communications. Due to the outstanding characteristics of Low-Density Parity-Check (LDPC) codes such as high decoding performance, high throughput, low complexity, they have been accepted as the standard codes for the 5G NR. In this paper, we propose two LDPC decoding algorithms: Hybrid Offset Min-Sum (HOMS) and Variable Offset Min-Sum (VOMS), which are aimed at improving the error correction performance. The main idea of the HOMS/VOMS algorithm is to apply modified factors to both variable-nodes and check-nodes updated processing in order to compensate the extrinsic messages overestimation of the MS-based algorithms and increase the protection ability for degree-1 variable-nodes. The simulation results show that at the Bit-Error-Rate (BER) of 10-5, the proposed HOMS/VOMS algorithm achieves the decoding gain up to 0.2 dB compared to the Offset Min-Sum (OMS) algorithm, with a slight increase in decoding complexity.