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En komparativ studie av sekventiell och SYCL-baserad QC-LDPC-avkodning för 5G NR

Anton Nyberg

Published Jan 1, 2026• 0 citations
OpenAlex

Abstract

Modern 5G New Radio (NR) systems demand high data rates, low delays, and consistent reliability, particularly in Cloud-Based Radio Access Network (C-RAN) where standard hardware handles signal processing. To meet these requirements, 5G NR uses Low-Density Parity-Check (LDPC) codes for channel coding. Although LDPC codes provide robust error correction, decoding them is computationally intensive. Consequently, achieving efficient LDPC software decoding is a significant obstacle in creating high-performing and adaptable 5G systems. Previous research has shown that performing Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoding in parallel on Graphics Processing Units (GPUs) using proprietary tools like CUDA can yield much higher performance than sequential Central Processing Unit (CPU) approaches. However, relying on such solutions can result in vendor lock-in and reduce portability across hardware platforms. This thesis investigates whether SYCL, a hardware-agnostic parallel programming framework based on C++, can provide efficient QC-LDPC decoding suitable for 5G NR C-RAN environments. This work introduces a QC-LDPC decoder implemented in SYCL that utilizes the Layered Offset Min-Sum algorithm. Its performance is evaluated against a comparable sequential C++ version and a CUDA-based GPU implementation. The experiments employ simulated 5G NR data, varying message sizes, base graph configurations, and channel conditions. The findings indicate that SYCL enables the code to operate on both CPUs and GPUs, though its effectiveness depends on the underlying hardware and specific workloads. On CPUs, SYCL does not surpass the sequential approach due to additional runtime overhead. On GPUs, SYCL shows advantages in the most computationally intensive decoding scenarios but still lags behind native CUDA implementations. These out comes highlight key trade-offs among performance, portability, and reliance on specific vendors when selecting programming models for QC-LDPC decoding in 5G systems.

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Paralleliserad QC-LDPC-avkodare pa en GPU : En utvardering av LDPC-koder som foljer 5G-standarden

Hedlund, Olivia

Over the last ten years, there has been an incremental growth of mobile network data traffic. The evolution leading to the development of 5G stands as a testament to the increased demands for high speed networks. Channel coding plays a pivotal role in 5G networks, making it possible to recover messages from errors introduced when sent through the network. Channel decoding is however a time consuming task for a receiver, and making optimization to this process could therefore have a significant impact on receiver processing time. Low-Density Parity-Check (LDPC) codes are one of the channel coding schemes used in the 5G standard. These codes could benefit from parallel processing, making Graphics Processing Units (GPUs) with their parallel computation abilities a possible platform for effective LDPC decoding. In this thesis, our goal is to evaluate a GPU as a platform for 5G LDPC decoding. The LDPC codes adhering to the 5G standard belong to the Quasi-Cyclic LDPC (QC-LDPC) subclass. Optimizations targeting this subclass, as well as other optimization techniques, are implemented in our thesis project to promote fast execution times. A GPU-based decoder is evaluated against a Central Processing Unit (CPU)-based decoder, written with Compute Unified Device Architecture (CUDA) and C++ respectively. The functionally equivalent decoders implement the layered offset Min-Sum Algorithm (MSA) with early termination to decode messages. Execution time for the decoders were measured while varying message size, Signal-to-Noise Ratio (SNR) and maximum iterations. Additionaly, we evaluated the decoders with and without including early termination, and also evaluated the GPU-decoder when it was integrated into a MATLAB 5G channel simulator used by Tietoevry. The results from the experiments showed that the GPU-based decoder experienced up to 4.3 times faster execution than the CPU-based decoder for message sizes ranging from 3000-12000 bits. The GPU-based decoder however experienced a higher baseline execution time, making the CPU-based decoder faster for smaller message sizes. It was also concluded that the benefit of including early termination in the decoder generally outweighs the cost of additional processing time.

•Jan 1, 2024•0 citations

Implementering och optimering av LDPC avkodningsalgoritmer anpassat för Nvidia GPU:er i 5G

Salomonsson, Benjamin

Low-Density Parity-Check (LDPC) codes are linear error-correcting codes used to establish reliable communication between units on a noisy transmission channel in mobile telecommunications. LDPC algorithms detect and recover altered or corrupted message bits using sparse parity-check matrices in order to decipher messages correctly. LDPC codes have been shown to be fitting coding schemes for the fifth generation (5G) New Radio (NR), according to the third generation partnership project (3GPP). TietoEvry, a consultant in telecom, has discovered that optimizations of LDPC decoding algorithms can be achieved/obtained with the use of a parallel computing platform called Compute Unified Device Architecture (CUDA), developed by NVIDIA. This platform utilizes the capabilities of a graphics processing unit (GPU) rather than a central processing unit (CPU), which in turn provides parallel computing. An optimized version of an LDPC decoding algorithm, the Min-Sum Algorithm (MSA), is implemented in CUDA and in C++ for comparison in terms of CPU execution time, to explore the capabilities that CUDA offers. The testing is done with a set of 12 sparse parity-check matrices and input-channel messages with different sizes. As a result, the CUDA implementation executes approximately 55% faster than a standard, unoptimized C++ implementation.

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This thesis investigates the acceleration of Low-Density Parity-Check (LDPC) decoding for 5G New Radio (5G NR) communication systems using NVIDIA Graphics Processing Units (GPUs) and the NVIDIA Sionna simulation framework. LDPC codes are widely used in modern wireless communication systems, including 5G NR, because of their strong error-correction capabilities. However, the decoding process is computationally intensive since it relies on iterative algorithms that require multiple rounds of calculations before a final decoding decision can be made. As communication systems continue to demand higher data rates and lower latency, improving the efficiency of LDPC decoding has become increasingly important. A complete LDPC-based communication system was implemented using Sionna. The system included Cyclic Redundancy Check (CRC) encoding, LDPC encoding, modulation, transmission through an Additive White Gaussian Noise (AWGN) channel, demodulation, LDPC decoding, and CRC decoding. Three LDPC decoding algorithms were evaluated: Sum-Product Algorithm (SPA), Min-Sum Algorithm (MSA), and Offset Min-Sum Algorithm (OMSA). The study focused on measuring decoding performance on NVIDIA GPUs and investigating optimization techniques that could reduce LDPC decoding execution time while maintaining reliable decoding performance. Two optimization techniques were implemented and evaluated: CRC-based early termination and Accelerated Linear Algebra (XLA) graph compilation. Early termination allowed the LDPC decoder to stop before reaching the maximum number of decoding iterations. XLA was used to improve the efficiency of the computations executed during LDPC decoding. The performance of the optimized implementations was compared with a baseline implementation across different signal-to-noise ratio (SNR) values. The results showed that both optimization techniques reduced decoding execution time, while maintaining reliable Block Error Rate (BLER) performance compared to the baseline scheme.

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This thesis presents a study on implementing a low-density parity-check (LDPC) decoder on a graphics processing unit (GPU) for 5G New Radio (NR). The proposed modifications include distributed execution configuration, compressed parity-check matrices (PCM) and message passing matrices to save memory space and applying the optimal iteration limit to the decoder. The performance of the LDPC decoder is evaluated using various testing cases with different algorithms, code rates and transport block sizes. The results show that the proposed decoder has more than 5× decoding speedup improvement on the short codes and more than 20× decoding speedup improvement on the long codes, while maintaining the error-correction performance. The optimal iteration limit is found to depend on the specific code rate and transport block size. The layered scheduling is a viable option on short codes over noisy channels.

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Accelerate QC-LDPC FEC for High-Throughput 5G/6G Wireless & Satellite on CPU and GPU SDRs

Vasiliy S. Usatyuk, Егоров Сергей Иванович

This paper presents a high-throughput decoding method for quasi-cyclic low-density parity-check (QC-LDPC) codes, optimized for both CPU and GPU-based Software-Defined Radios (SDRs). The approach leverages a SIMD data alignment architecture that minimizes cache misses and is designed to take full advantage of modern CPUs and GPUs with rich registers and caches. An innovative decoding algorithm is introduced, exploiting the SIMD capabilities of contemporary CPUs to enhance parallelism, while optimizing memory access patterns to align SIMD operations and minimize branching and cache misses on AMD EPYC CPUs (2xEPYC-9754). This results in significant throughput improvements. The method is further extended to GPUs, utilizing their large-scale parallelism through efficient use of registers and local memory. To maximize performance, a memory-efficient check node decoding strategy is employed, ensuring that operations fit within the cache of the Streaming Multiprocessors (SM) to reduce memory access overhead. Simulation results demonstrate the effectiveness of this approach: the CPU-based 8-iteration layered min-sum decoder with early termination achieves coded bit throughputs of up to 72.9 Gbps for 16200-bit codes and 50.9 Gbps for 64800-bit DVB-S2 QC-LDPC codes. On GPUs, the decoder reaches 132 Gbps for short 802.11n Wi-Fi 1944-bit codes and 22.3 Gbps for 5G Base Graph 1 26112-bit codes on an NVIDIA RTX 4090. For 6G prototype QC-LDPC codes, the proposed 3-layer design achieves up to 76 Gbps for 1920-bit codes, with surpassing 104 Gbps on the NVIDIA RTX 5090. Compared to the open-source AFF3CT CPU framework, the proposed method offers 5 to 12 times higher throughput across various code lengths. Even when AFF3CT is optimized with MIPP intrinsics, the new decoder provides 3.2 to 5.7 times better throughput. The GPU implementation delivers up to 120 times the speed of previously published results and offers 13 to 40 times improvement over older GPUs like the GTX 1080 Ti and Titan X, scaling effectively with modern GPUs like the RTX 4090. This approach establishes new performance benchmarks for QC-LDPC decoding, positioning it as an ideal solution for next-generation 5G/6G wireless and satellite communications.

International Conference on Digital Signal Processing and its Applications (DSPA)•Mar 26, 2025•1 citation

An Efficient QC-LDPC Decoder Architecture for 5G-NR Wireless Communication Standards Targeting FPGA

Bilal Mejmaa, Malika Alami Marktani, Ismail Akharraz +1 more

This novel research introduces a game-changing architecture design for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoders in Fifth-Generation New-Radio (5G-NR) wireless communications, specifically designed to meet precise specifications and leveraging the layered Min-Sum (MS) algorithm. Our innovative approach presents a fully parallel architecture that is precisely engineered to cater to the demanding high-throughput requirements of enhanced Mobile Broadband (eMBB) applications. To ensure smooth computation in the MS algorithm, we use the Sub-Optimal Low-Latency (SOLL) technique to optimize the critical check node process. Thus, our design has the potential to greatly benefit certain Ultra-Reliable Low-Latency Communications (URLLC) scenarios. We conducted precise Bit Error Rate (BER) performance analysis on our LDPC decoder using a Hardware Description Language (HDL) Co-Simulation (MATLAB/Simulink/ModelSim) for two codeword rates (2/3 and 1/3), simulating the challenging Additive White Gaussian Noise (AWGN) channel environment.

Computers•Aug 14, 2024•11 citations
Modern 5G New Radio (NR) systems demand high data rates, low delays, and consistent reliability, particularly in Cloud-Based Radio Access Network (C-RAN) where standard hardware handles signal processing. To meet these requirements, 5G NR uses Low-Density Parity-Check (LDPC) codes for channel coding. Although LDPC codes provide robust error correction, decoding them is computationally intensive. Consequently, achieving efficient LDPC software decoding is a significant obstacle in creating high-performing and adaptable 5G systems. Previous research has shown that performing Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoding in parallel on Graphics Processing Units (GPUs) using proprietary tools like CUDA can yield much higher performance than sequential Central Processing Unit (CPU) approaches. However, relying on such solutions can result in vendor lock-in and reduce portability across hardware platforms. This thesis investigates whether SYCL, a hardware-agnostic parallel programming framework based on C++, can provide efficient QC-LDPC decoding suitable for 5G NR C-RAN environments. This work introduces a QC-LDPC decoder implemented in SYCL that utilizes the Layered Offset Min-Sum algorithm. Its performance is evaluated against a comparable sequential C++ version and a CUDA-based GPU implementation. The experiments employ simulated 5G NR data, varying message sizes, base graph configurations, and channel conditions. The findings indicate that SYCL enables the code to operate on both CPUs and GPUs, though its effectiveness depends on the underlying hardware and specific workloads. On CPUs, SYCL does not surpass the sequential approach due to additional runtime overhead. On GPUs, SYCL shows advantages in the most computationally intensive decoding scenarios but still lags behind native CUDA implementations. These out comes highlight key trade-offs among performance, portability, and reliance on specific vendors when selecting programming models for QC-LDPC decoding in 5G systems.
Over the last ten years, there has been an incremental growth of mobile network data traffic. The evolution leading to the development of 5G stands as a testament to the increased demands for high speed networks. Channel coding plays a pivotal role in 5G networks, making it possible to recover messages from errors introduced when sent through the network. Channel decoding is however a time consuming task for a receiver, and making optimization to this process could therefore have a significant impact on receiver processing time. Low-Density Parity-Check (LDPC) codes are one of the channel coding schemes used in the 5G standard. These codes could benefit from parallel processing, making Graphics Processing Units (GPUs) with their parallel computation abilities a possible platform for effective LDPC decoding. In this thesis, our goal is to evaluate a GPU as a platform for 5G LDPC decoding. The LDPC codes adhering to the 5G standard belong to the Quasi-Cyclic LDPC (QC-LDPC) subclass. Optimizations targeting this subclass, as well as other optimization techniques, are implemented in our thesis project to promote fast execution times. A GPU-based decoder is evaluated against a Central Processing Unit (CPU)-based decoder, written with Compute Unified Device Architecture (CUDA) and C++ respectively. The functionally equivalent decoders implement the layered offset Min-Sum Algorithm (MSA) with early termination to decode messages. Execution time for the decoders were measured while varying message size, Signal-to-Noise Ratio (SNR) and maximum iterations. Additionaly, we evaluated the decoders with and without including early termination, and also evaluated the GPU-decoder when it was integrated into a MATLAB 5G channel simulator used by Tietoevry. The results from the experiments showed that the GPU-based decoder experienced up to 4.3 times faster execution than the CPU-based decoder for message sizes ranging from 3000-12000 bits. The GPU-based decoder however experienced a higher baseline execution time, making the CPU-based decoder faster for smaller message sizes. It was also concluded that the benefit of including early termination in the decoder generally outweighs the cost of additional processing time.
Low-Density Parity-Check (LDPC) codes are linear error-correcting codes used to establish reliable communication between units on a noisy transmission channel in mobile telecommunications. LDPC algorithms detect and recover altered or corrupted message bits using sparse parity-check matrices in order to decipher messages correctly. LDPC codes have been shown to be fitting coding schemes for the fifth generation (5G) New Radio (NR), according to the third generation partnership project (3GPP). TietoEvry, a consultant in telecom, has discovered that optimizations of LDPC decoding algorithms can be achieved/obtained with the use of a parallel computing platform called Compute Unified Device Architecture (CUDA), developed by NVIDIA. This platform utilizes the capabilities of a graphics processing unit (GPU) rather than a central processing unit (CPU), which in turn provides parallel computing. An optimized version of an LDPC decoding algorithm, the Min-Sum Algorithm (MSA), is implemented in CUDA and in C++ for comparison in terms of CPU execution time, to explore the capabilities that CUDA offers. The testing is done with a set of 12 sparse parity-check matrices and input-channel messages with different sizes. As a result, the CUDA implementation executes approximately 55% faster than a standard, unoptimized C++ implementation.
This thesis investigates the acceleration of Low-Density Parity-Check (LDPC) decoding for 5G New Radio (5G NR) communication systems using NVIDIA Graphics Processing Units (GPUs) and the NVIDIA Sionna simulation framework. LDPC codes are widely used in modern wireless communication systems, including 5G NR, because of their strong error-correction capabilities. However, the decoding process is computationally intensive since it relies on iterative algorithms that require multiple rounds of calculations before a final decoding decision can be made. As communication systems continue to demand higher data rates and lower latency, improving the efficiency of LDPC decoding has become increasingly important. A complete LDPC-based communication system was implemented using Sionna. The system included Cyclic Redundancy Check (CRC) encoding, LDPC encoding, modulation, transmission through an Additive White Gaussian Noise (AWGN) channel, demodulation, LDPC decoding, and CRC decoding. Three LDPC decoding algorithms were evaluated: Sum-Product Algorithm (SPA), Min-Sum Algorithm (MSA), and Offset Min-Sum Algorithm (OMSA). The study focused on measuring decoding performance on NVIDIA GPUs and investigating optimization techniques that could reduce LDPC decoding execution time while maintaining reliable decoding performance. Two optimization techniques were implemented and evaluated: CRC-based early termination and Accelerated Linear Algebra (XLA) graph compilation. Early termination allowed the LDPC decoder to stop before reaching the maximum number of decoding iterations. XLA was used to improve the efficiency of the computations executed during LDPC decoding. The performance of the optimized implementations was compared with a baseline implementation across different signal-to-noise ratio (SNR) values. The results showed that both optimization techniques reduced decoding execution time, while maintaining reliable Block Error Rate (BLER) performance compared to the baseline scheme.
This thesis presents a study on implementing a low-density parity-check (LDPC) decoder on a graphics processing unit (GPU) for 5G New Radio (NR). The proposed modifications include distributed execution configuration, compressed parity-check matrices (PCM) and message passing matrices to save memory space and applying the optimal iteration limit to the decoder. The performance of the LDPC decoder is evaluated using various testing cases with different algorithms, code rates and transport block sizes. The results show that the proposed decoder has more than 5× decoding speedup improvement on the short codes and more than 20× decoding speedup improvement on the long codes, while maintaining the error-correction performance. The optimal iteration limit is found to depend on the specific code rate and transport block size. The layered scheduling is a viable option on short codes over noisy channels.
This paper presents a high-throughput decoding method for quasi-cyclic low-density parity-check (QC-LDPC) codes, optimized for both CPU and GPU-based Software-Defined Radios (SDRs). The approach leverages a SIMD data alignment architecture that minimizes cache misses and is designed to take full advantage of modern CPUs and GPUs with rich registers and caches. An innovative decoding algorithm is introduced, exploiting the SIMD capabilities of contemporary CPUs to enhance parallelism, while optimizing memory access patterns to align SIMD operations and minimize branching and cache misses on AMD EPYC CPUs (2xEPYC-9754). This results in significant throughput improvements. The method is further extended to GPUs, utilizing their large-scale parallelism through efficient use of registers and local memory. To maximize performance, a memory-efficient check node decoding strategy is employed, ensuring that operations fit within the cache of the Streaming Multiprocessors (SM) to reduce memory access overhead. Simulation results demonstrate the effectiveness of this approach: the CPU-based 8-iteration layered min-sum decoder with early termination achieves coded bit throughputs of up to 72.9 Gbps for 16200-bit codes and 50.9 Gbps for 64800-bit DVB-S2 QC-LDPC codes. On GPUs, the decoder reaches 132 Gbps for short 802.11n Wi-Fi 1944-bit codes and 22.3 Gbps for 5G Base Graph 1 26112-bit codes on an NVIDIA RTX 4090. For 6G prototype QC-LDPC codes, the proposed 3-layer design achieves up to 76 Gbps for 1920-bit codes, with surpassing 104 Gbps on the NVIDIA RTX 5090. Compared to the open-source AFF3CT CPU framework, the proposed method offers 5 to 12 times higher throughput across various code lengths. Even when AFF3CT is optimized with MIPP intrinsics, the new decoder provides 3.2 to 5.7 times better throughput. The GPU implementation delivers up to 120 times the speed of previously published results and offers 13 to 40 times improvement over older GPUs like the GTX 1080 Ti and Titan X, scaling effectively with modern GPUs like the RTX 4090. This approach establishes new performance benchmarks for QC-LDPC decoding, positioning it as an ideal solution for next-generation 5G/6G wireless and satellite communications.
This novel research introduces a game-changing architecture design for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoders in Fifth-Generation New-Radio (5G-NR) wireless communications, specifically designed to meet precise specifications and leveraging the layered Min-Sum (MS) algorithm. Our innovative approach presents a fully parallel architecture that is precisely engineered to cater to the demanding high-throughput requirements of enhanced Mobile Broadband (eMBB) applications. To ensure smooth computation in the MS algorithm, we use the Sub-Optimal Low-Latency (SOLL) technique to optimize the critical check node process. Thus, our design has the potential to greatly benefit certain Ultra-Reliable Low-Latency Communications (URLLC) scenarios. We conducted precise Bit Error Rate (BER) performance analysis on our LDPC decoder using a Hardware Description Language (HDL) Co-Simulation (MATLAB/Simulink/ModelSim) for two codeword rates (2/3 and 1/3), simulating the challenging Additive White Gaussian Noise (AWGN) channel environment.