Multi-channel quantum true random number generator based on CMOS and FPGA technologies

Jean‐Luc Danger, Sylvain Guilley, Philippe Hoogvorst

Abdullah Ash Saki, Mahabubul Alam, Swaroop Ghosh

Andrea Stanco, Davide G. Marangon, Giuseppe Vallone +3 more

Abstract True random number generators (TRNGs) allow the generation of true random bit sequences, guaranteeing the unpredictability and perfect balancing of the generated values. TRNGs can be realised from the sampling of quantum phenomena, for instance, the detection of single photons. Here, a recently proposed technique, which implements a quantum random number generator (QRNG) out of a device that was realised for a different scope, is further analysed and certified [1]. The combination of a CMOS single‐photon avalanche diode (SPAD) array, a high‐resolution time‐to‐digital converter (TDC) implemented on a field programmable gate array (FPGA), the exploitation of a single‐photon temporal degree of freedom, and an unbiased procedure provided by H. Zhou and J. Bruck [2, 3] allows the generation of true random bits with a high bitrate in a compact and easy‐to‐calibrate device. Indeed, the use of the ‘Zhou–Bruck’ method allows the removal of any correlation from the binary representation of decimal data. This perfectly fits with the usage of a device with non‐idealities like SPAD's afterpulses, pixel cross‐correlation, and time‐to‐digital converter non‐uniform conversion. In this work, an in‐depth analysis and certification of the technique presented in [1] is provided by processing the data with the NIST suite tests in order to prove the effectiveness and validity of this approach.

Yonggang Wang, Cong Hui, Chong Liu +1 more

The contribution of this paper is proposing a new entropy extraction mechanism based on sampling phase jitter in ring oscillators to make a high throughput true random number generator in a field programmable gate array (FPGA) practical. Starting from experimental observation and analysis of the entropy source in FPGA, a multi-phase sampling method is exploited to harvest the clock jitter with a maximum entropy and fast sampling speed. This parametrized design is implemented in a Xilinx Artix-7 FPGA, where the carry chains in the FPGA are explored to realize the precise phase shifting. The generator circuit is simple and resource-saving, so that multiple generation channels can run in parallel to scale the output throughput for specific applications. The prototype integrates 64 circuit units in the FPGA to provide a total output throughput of 7.68 Gbps, which meets the requirement of current high-speed quantum key distribution systems. The randomness evaluation, as well as its robustness to ambient temperature, confirms that the new method in a purely digital fashion can provide high-speed high-quality random bit sequences for a variety of embedded applications.

Hamid Tebyanian

Jian Wang, Xu Wan, Hongfei Zhang +3 more