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Review of Scientific Instruments

Theory and implementation of a very high throughput true random number generator in field programmable gate array

Yonggang Wang, Cong Hui, Chong Liu, Chao Xu

Published Apr 1, 2016• 21 citations
Publisher

Abstract

The contribution of this paper is proposing a new entropy extraction mechanism based on sampling phase jitter in ring oscillators to make a high throughput true random number generator in a field programmable gate array (FPGA) practical. Starting from experimental observation and analysis of the entropy source in FPGA, a multi-phase sampling method is exploited to harvest the clock jitter with a maximum entropy and fast sampling speed. This parametrized design is implemented in a Xilinx Artix-7 FPGA, where the carry chains in the FPGA are explored to realize the precise phase shifting. The generator circuit is simple and resource-saving, so that multiple generation channels can run in parallel to scale the output throughput for specific applications. The prototype integrates 64 circuit units in the FPGA to provide a total output throughput of 7.68 Gbps, which meets the requirement of current high-speed quantum key distribution systems. The randomness evaluation, as well as its robustness to ambient temperature, confirms that the new method in a purely digital fashion can provide high-speed high-quality random bit sequences for a variety of embedded applications.

DOI
10.1063/1.4945564

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The contribution of this paper is proposing a new entropy extraction mechanism based on sampling phase jitter in ring oscillators to make a high throughput true random number generator in a field programmable gate array (FPGA) practical. Starting from experimental observation and analysis of the entropy source in FPGA, a multi-phase sampling method is exploited to harvest the clock jitter with a maximum entropy and fast sampling speed. This parametrized design is implemented in a Xilinx Artix-7 FPGA, where the carry chains in the FPGA are explored to realize the precise phase shifting. The generator circuit is simple and resource-saving, so that multiple generation channels can run in parallel to scale the output throughput for specific applications. The prototype integrates 64 circuit units in the FPGA to provide a total output throughput of 7.68 Gbps, which meets the requirement of current high-speed quantum key distribution systems. The randomness evaluation, as well as its robustness to ambient temperature, confirms that the new method in a purely digital fashion can provide high-speed high-quality random bit sequences for a variety of embedded applications.
High-speed true random number generator is a building block in the modern information security system. We propose and demonstrate an efficient high-speed true random number generator based on multiple parallel self-timed rings (STRs). To improve the security, we evaluate the randomness of the entropy source by min-entropy and exploit the information-theoretically provable Toeplitz-hashing extractor. To minimize the consumption of hardware resources of a field programmable gate array at a predetermined high throughput and maximize the throughput with the limited hardware resources, we systematically derive and investigate the dependence of the data throughput and the total consumed resources of the random number generator on the system parameters. On this basis, we make a joint optimization for the degree of parallelism of the STRs and the extraction efficiency of the extractor. A 10-Gbps true random number generator is implemented efficiently, so that the output random bits can pass all the National Institute of Standards and Technology (NIST) and Dieharder test suites.
Most hardware "true" random number generators (TRNGs) take advantage of the thermal agitation around a flip-flop metastable state. In field programmable gate arrays (FPGAs), the classical TRNG structure uses two clocks, either from a PLL or from ring oscillators, in order to sample one by the other. This creates good TRNGs albeit limited in frequency by the interference rate which cannot exceed a few Mbit/s. This article presents an architecture allowing higher bit rates while maintaining provable unconditional security. This requirement becomes stringent for secure communication applications such as the cryptographic quantum key distribution (QKD) protocols. The proposed architecture is very simple as it is based on an open loop structure without any specific component such as PLLs.
We present a random number generation scheme based on measuring the phase fluctuations of a laser with a simple experimental setup. A simple model is established to analyze the randomness and the simulation result based on this model fits well with the experiment data. After the analog to digital sampling and suitable randomness extraction integrated in the field programmable gate array, the final random bits are delivered to a PC, realizing a 5.4 Gbps real time quantum random number generation. The final random bit sequences have passed all the NIST and DIEHARD tests.
Based on the research of the current situation of continuous variables quantum cryptographic key QCK and in order to guarantee the effect of communication, we aim to build a quantum communication system based on Reverse Reconciliation Protocol. Thus, a good Gaussian Random Number Generator based on FPGA (Field Programmable Gate Array) is proposed in this paper which can run fast and acquire a high throughput per slice. In this paper, Gaussian random number generator is based on the analysis of Box-Muller algorithm. Besides, seeds for Gaussian random number are input by mechanical keyboard which joggles randomly. Implementation results on Altera FPGA show that the proposed hardware design could generate Gaussian random number with period of 232−12^{32}-1232−1. Finally, we get the mean values, variances, maximum deviations and distribution diagrams of the generated Gaussian random numbers(GRN) by importing these data into Matlab. To assess the quality of these generated GRN, we further compare them to these GRN generated by Matlab.
We demonstrate a method to generate application-ready truly random bits from a magnetic tunnel junction driven by a Field-Programmable Gate Array (FPGA). We implement a real-time feedback loop that stabilizes the switching probability near 50% and apply an XOR operation, both on the FPGA, to suppress short-term correlations, together mitigating long-term drift and bias in the bitstream. This combined approach passes the NIST Statistical Test Suite for random bit generation at 5 Mb/s without post-processing, providing a practical hardware solution for fast and reliable true random number generation. Beyond cryptographic applications, these capabilities open opportunities for stochastic hardware accelerators, probabilistic computing, and large-scale modeling where real-time access to unbiased randomness is essential.
Quantum Random Number Generators (QRNGs) serve as high entropy sources for Quantum Key Distribution (QKD) systems. The raw data from quantum sources however require post-processing to generate a nearly uniform distribution. This work presents a state-of-the-art implementation of the Toeplitz Strong Extractor on an FPGA, achieving a benchmark extraction speed of 26.57 Gbps. A detailed implementation flow of the post-processing on FPGA is presented along with the various execution speeds obtained based on different randomness extraction ratios. Raw data from an in-house phase noise-based QRNG is processed on the FPGA using the implementation and the output is validated via the NIST STS 2.1.2 statistical randomness tests suite.