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Microelectronics Journal

High speed true random number generator based on open loop structures in FPGAs

Jean‐Luc Danger, Sylvain Guilley, Philippe Hoogvorst

Published Apr 3, 2009• 102 citations
Publisher
DOI
10.1016/j.mejo.2009.02.004

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Most hardware "true" random number generators (TRNGs) take advantage of the thermal agitation around a flip-flop metastable state. In field programmable gate arrays (FPGAs), the classical TRNG structure uses two clocks, either from a PLL or from ring oscillators, in order to sample one by the other. This creates good TRNGs albeit limited in frequency by the interference rate which cannot exceed a few Mbit/s. This article presents an architecture allowing higher bit rates while maintaining provable unconditional security. This requirement becomes stringent for secure communication applications such as the cryptographic quantum key distribution (QKD) protocols. The proposed architecture is very simple as it is based on an open loop structure without any specific component such as PLLs.
High-speed true random number generator is a building block in the modern information security system. We propose and demonstrate an efficient high-speed true random number generator based on multiple parallel self-timed rings (STRs). To improve the security, we evaluate the randomness of the entropy source by min-entropy and exploit the information-theoretically provable Toeplitz-hashing extractor. To minimize the consumption of hardware resources of a field programmable gate array at a predetermined high throughput and maximize the throughput with the limited hardware resources, we systematically derive and investigate the dependence of the data throughput and the total consumed resources of the random number generator on the system parameters. On this basis, we make a joint optimization for the degree of parallelism of the STRs and the extraction efficiency of the extractor. A 10-Gbps true random number generator is implemented efficiently, so that the output random bits can pass all the National Institute of Standards and Technology (NIST) and Dieharder test suites.
The contribution of this paper is proposing a new entropy extraction mechanism based on sampling phase jitter in ring oscillators to make a high throughput true random number generator in a field programmable gate array (FPGA) practical. Starting from experimental observation and analysis of the entropy source in FPGA, a multi-phase sampling method is exploited to harvest the clock jitter with a maximum entropy and fast sampling speed. This parametrized design is implemented in a Xilinx Artix-7 FPGA, where the carry chains in the FPGA are explored to realize the precise phase shifting. The generator circuit is simple and resource-saving, so that multiple generation channels can run in parallel to scale the output throughput for specific applications. The prototype integrates 64 circuit units in the FPGA to provide a total output throughput of 7.68 Gbps, which meets the requirement of current high-speed quantum key distribution systems. The randomness evaluation, as well as its robustness to ambient temperature, confirms that the new method in a purely digital fashion can provide high-speed high-quality random bit sequences for a variety of embedded applications.