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International SoC Design Conference

Thermal Analysis of SFQ Circuits Designed for the ADP2 Fabrication Process

Asahi Saito, Pratiksha Mundhe, Iori Ishikawa, Koji Inoue, Ilkwon Byun

Published Oct 15, 2025• 0 citations
Publisher

Abstract

Superconductor single-flux-quantum (SFQ) logic requires careful thermal analysis to realize its potential in high-performance and low-power computing. However, the thermal behavior of SFQ circuits remains underexplored and limited to a specific fabrication process. To complement the limited analy-sis, this work conducts the first thermal analysis of SFQ circuits designed for the ADP2 fabrication process. Based on our analysis, we present various discussions on the thermal behavior of SFQ circuits using the recently demonstrated fabrication process.

DOI
10.1109/isocc66390.2025.11329859

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Superconductor single-flux-quantum (SFQ) logic requires careful thermal analysis to realize its potential in high-performance and low-power computing. However, the thermal behavior of SFQ circuits remains underexplored and limited to a specific fabrication process. To complement the limited analy-sis, this work conducts the first thermal analysis of SFQ circuits designed for the ADP2 fabrication process. Based on our analysis, we present various discussions on the thermal behavior of SFQ circuits using the recently demonstrated fabrication process.
Single flux quantum (SFQ) logic circuits, in which a single flux quantum is used for an information carrier, have a possibility to open a new digital system operated with over 100 GHz clock frequencies at extremely low power dissipations. Recently, much progress in basic technologies for designing SFQ circuits and operating circuits with high speeds has been done. By taking advancements in these designing tools, circuits including more than several thousands junctions easily operated with the clock frequency of more than several tens GHz. Applications of SFQ circuits such as high performance computers, high end router and high end servers are being developed in the world taking advantages of the high through-put nature and the low power dissipation of the SFQ logic.
Superconductor single-flux-quantum (SFQ) integrated circuits can provide classical, general-purpose digital processing at cryogenic temperature near quantum bits. We report high-frequency operation of low-power SFQ circuits using a lowered critical current density fabrication process and low-voltage design. We are developing a standard-cell library with integrated devices featuring four planarized Nb layers and a Pd resistor layer. SFQ shift registers successfully operated at up to 11 GHz at 0.3 K. The measured operating frequency is sufficient for SFQ-based digital controlling of quantum bits using impulse-shaped voltage pulses.
Single Flux Quantum (SFQ) electronic circuits originated with the advent of Rapid Single Flux Quantum (RSFQ) logic in 1985 and have since evolved to include more energy-efficient technologies such as ERSFQ and eSFQ. SFQ logic circuits, based on the manipulation of quantized flux pulses, have been demonstrated to run at clock speeds in excess of 120 GHz, and with bit-switch energy below 1 aJ. Small SFQ microprocessors have been developed, but characteristics inherent to SFQ circuits and the lack of circuit design tools have hampered the development of large SFQ systems. SFQ circuit characteristics include fan-out of one and the subsequent demand for pulse splitters, gate-level clocking, susceptibility to magnetic fields and sensitivity to intra-gate and inter-gate inductance. Superconducting interconnects propagate data pulses at the speed of light, but suffer from reflections at vias that attenuate transmitted pulses. The recently started IARPA SuperTools program aims to deliver SFQ Computer-Aided Design (CAD) tools that can enable the successful design of 64 bit RISC processors given the characteristics of SFQ circuits. A discussion on the technology of SFQ circuits and the most modern SFQ fabrication processes is presented, with a focus on the unique electronic design automation CAD requirements for the design, layout and verification of SFQ circuits.
We report low-power single-flux-quantum (SFQ) circuits fabricated with a lowered critical current density process and low-voltage design. We selected 250 A/cm2^{2}2to obtain 2–10 μA Josephson junctions (JJs) easily using conventional facilities. Our numerical simulation shows that the expected operating frequency is 10 GHz and that we can reduce the bias voltage to 0.1–0.5 mV; power consumption can be reduced to around 1 nW per JJ. We newly developed a fabrication process featuring four planarized Nb layers and a Pd resistor layer. We obtained the correct operation of several basic SFQ circuit elements designed with the lowered critical currents to 1/2 of the conventional circuits at 4.2 K. We also evaluated the Josephson junction critical currents, specific capacitance, resistance, and inductance at 3 K and 300 mK. We observed an increase of 7% in the critical currents at 300 mK, while the other parameters were unchanged. We demonstrated a 0.5-mV Josephson transmission line where we lowered the critical currents to 1/10. We expect such low-power SFQ circuits to operate at 20 mK, providing classical, general-purpose digital processing near quantum bits.
CMOS microprocessors are limited in their capacity for clock speed improvement because of increasing computing power, i.e., they face a power-wall problem. Single-flux-quantum (SFQ) circuits offer a solution with their ultra-fast-speed and ultra-low-power natures. This paper introduces our contributions towards ultra-high-speed cryogenic SFQ computing. The first step is to design SFQ microprocessors. From qualitatively and quantitatively evaluating past-designed SFQ microprocessors, we have found that revisiting the architecture of SFQ microprocessors and on-chip caches is the first critical challenge. On the basis of cross-layer discussions and analysis, we came to the conclusion that a bit-parallel gate-level pipeline architecture is the best solution for SFQ designs. This paper summarizes our current research results targeting SFQ microprocessors and on-chip cache architectures.