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Physical Review Letters

Experimental Quantum Error Correction below the Surface Code Threshold via All-Microwave Leakage Suppression

Tan He, W. W. Lin, Rui Wang, Yuan Li, Jiahao Bei, Jianbin Cai, Sirui Cao, Danning Chen, K.Y. Chen, Xiawei Chen, Zhe Chen, Zhiyuan Chen, Zihua Chen, Wenhao Chu, Hui Deng, Xun Ding, Zhuzhengqi Ding, Bo Fan, Daojin Fan, Yuanhao Fu, Dongxin Gao, Ming Gong, Jiacheng Gui, Cheng Guo, Shaojun Guo, Lianchen Han, Linyin Hong, Yisen Hu, He-Liang Huang, Yong-Heng Huo, C. P. Jiang, Lei Jiang, Tao Jiang, Zuokai Jiang, Honghong Jin, Dayu Li, Dongdong Li, Jiaqi Li, Jinjin Li, Junyan Li, J.F. Li, Na Li, Shaowei Li, Yuhuai Li, Futian Liang, Nanxing Liao, Jin Lin, Ke Liu, Maliang Liu, Yancheng Liu, Haoxin Lou, Yuwei Ma, Kailiang Nan, M. Nie, Le Niu, Wenyi Peng, Haoran Qian, Hao Rong, Rong Tao, Huiyan Shen, Qiong Shen, Hong Su, Feifan Su, Chenyin Sun, Lihua Sun, Tianzuo Sun, Yingxiu Sun, Yimeng Tan, Jun Tan, Wenbing Tu, Jiafei Wang, Biao Wang, Chang Wang, Chen Wang, Chu Wang, Jian Wang, Shengtao Wang, Xinzhe Wang, Zuolin Wei, Dachao Wu, Gang Wu, Yulin Wu, Yu Xu, Chun Jason Xue, Kai Yan, Xin Yan, Weifeng Yang, Xinpeng Yang, Yang Yang, Y. Ye, Zhenping Ye, Zhengzhong Yi, Chong Ying, Jiale Yu, Qinjing Yu, Xiangdong Zeng, Chen Zha, Shaoyu Zhan, Haibin Zhang, He Zhang

Published Dec 22, 2025• 14 citations
Publisher

Abstract

Quantum error correction (QEC) enables practical quantum computing by encoding logical qubits in many physical qubits, which can exponentially suppress the logical error rate with increasing code size provided that the physical error rate is below a critical threshold. However, the leakage of quantum information from the computational subspace presents a critical challenge to the development of scalable QEC, which creates long-lived, correlated errors that spread across space and time. Here, we demonstrate a quantum memory operating below the threshold by implementing an all-microwave leakage suppression architecture on a distance-7 surface code. We achieve a logical error suppression factor of Λ=1.40(6), definitively reversing the above-threshold scaling (Λ<1) caused by unmitigated leakage. This scheme integrates a hardware-efficient leakage reduction unit for data qubits with a fast, unconditional reset for ancilla qubits, suppressing the average leakage population after 40 cycles by a factor of 72 to 6.4(5)×10^{-4}. Our results demonstrate the viability of all-microwave control architectures for suppressing critical errors at scale, paving the way for more advanced quantum error correction implementations.

DOI
10.1103/rqkg-dw31

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Quantum error correction (QEC) enables practical quantum computing by encoding logical qubits in many physical qubits, which can exponentially suppress the logical error rate with increasing code size provided that the physical error rate is below a critical threshold. However, the leakage of quantum information from the computational subspace presents a critical challenge to the development of scalable QEC, which creates long-lived, correlated errors that spread across space and time. Here, we demonstrate a quantum memory operating below the threshold by implementing an all-microwave leakage suppression architecture on a distance-7 surface code. We achieve a logical error suppression factor of Λ=1.40(6), definitively reversing the above-threshold scaling (Λ<1) caused by unmitigated leakage. This scheme integrates a hardware-efficient leakage reduction unit for data qubits with a fast, unconditional reset for ancilla qubits, suppressing the average leakage population after 40 cycles by a factor of 72 to 6.4(5)×10^{-4}. Our results demonstrate the viability of all-microwave control architectures for suppressing critical errors at scale, paving the way for more advanced quantum error correction implementations.
Leakage outside of the qubit computational subspace poses a threatening challenge to quantum error correction (QEC).We propose a scheme using two leakage-reduction units (LRUs) that mitigate these issues for a transmon-based surface code, without requiring an overhead in terms of hardware or QECcycle time as in previous proposals.For data qubits, we consider a microwave drive to transfer leakage to the readout resonator, where it quickly decays, ensuring that this negligibly disturbs the computational states for realistic system parameters.For ancilla qubits, we apply a |1 ↔ |2 π pulse conditioned on the measurement outcome.Using density-matrix simulations of the distance-3 surface code, we show that the average leakage lifetime is reduced to almost one QEC cycle, even when the LRUs are implemented with limited fidelity.Furthermore, we show that this leads to a significant reduction of the logical error rate.This LRU scheme opens the prospect for near-term scalable QEC demonstrations.
Quantum error correction can suppress logical errors exponentially with code distance when physical noise is below threshold. Realizing this on hardware requires tight coordination among quantum gates, mid-circuit measurements, and qubit coherence. Device variation, noise asymmetry, and correlations across space and time complicate the translation of these capabilities into logical error suppression. Here, we study rotated surface-code memory on an IBM Nighthawk r2 processor. Performance varies across tested processor placements, which we attribute to differences in qubit quality. We optimize the code by combining short readout, fused measurement and reset, and an XX echo on data qubits during ancilla readout. Compared with standard readout without reset or echo, the optimized syndrome extraction circuit reduces the median per-round logical error rate by factors of 3.8 in the X basis and 1.4 in the Z basis. In memory experiments of up to 150 rounds, the distance advantage weakens, alongside long-lived correlations that may reflect a persistent error component. Under our optimization recipe, increasing the protected distance from 3 to 6 while holding the other distance fixed reduces the per-round logical error rate from 0.53% to 0.24% in Z memory and from 0.52% to 0.22% in X memory. The corresponding error-suppression factors under maximum-likelihood decoding are 1.68 and 1.85. These results connect circuit compilation and optimization to surface-code memory performance and limitations, and motivate QPU and QEC circuit codesign for fault-tolerant quantum computing primitives on current cloud hardware.
Abstract The leakage of quantum information out of the two computational states of a qubit into other energy states represents a major challenge for quantum error correction. During the operation of an error-corrected algorithm, leakage builds over time and spreads through multi-qubit interactions. This leads to correlated errors that degrade the exponential suppression of the logical error with scale, thus challenging the feasibility of quantum error correction as a path towards fault-tolerant quantum computation. Here, we demonstrate a distance-3 surface code and distance-21 bit-flip code on a quantum processor for which leakage is removed from all qubits in each cycle. This shortens the lifetime of leakage and curtails its ability to spread and induce correlated errors. We report a tenfold reduction in the steady-state leakage population of the data qubits encoding the logical state and an average leakage population of less than 1 × 10 −3 throughout the entire device. Our leakage removal process efficiently returns the system back to the computational basis. Adding it to a code circuit would prevent leakage from inducing correlated error across cycles. With this demonstration that leakage can be contained, we have resolved a key challenge for practical quantum error correction at scale.
Quantum error correction [1, 2, 3, 4] provides a path to reach practical quantum computing by combining multiple physical qubits into a logical qubit, where the logical error rate is suppressed exponentially as more qubits are added. However, this exponential suppression only occurs if the physical error rate is below a critical threshold. Here, we present two below-threshold surface code memories on our newest generation of superconducting processors, Willow: a distance-7 code, and a distance-5 code integrated with a real-time decoder. The logical error rate of our larger quantum memory is suppressed by a factor of Λ=2.14±0.02\varLambda \mathrm{=2.14}\pm 0.02Λ=2.14±0.02 when increasing the code distance by two, culminating in a 101-qubit distance-7 code with 0.143% ± 0.003% error per cycle of error correction. This logical memory is also beyond break-even, exceeding its best physical qubit’s lifetime by a factor of 2.4±0.32.4\pm 0.32.4±0.3 . Our system maintains below-threshold performance when decoding in real time, achieving an average decoder latency of 63 μs at distance-5 up to a million cycles, with a cycle time of 1.1 μs. We also run repetition codes up to distance-29 and find that logical performance is limited by rare correlated error events occurring approximately once every hour, or 333 ×\times × 109{10}^{9}109 cycles. Our results present device performance that, if scaled, could realize the operational requirements of large scale fault-tolerant quantum algorithms.
Quantum error correction enables scalable fault-tolerant quantum computation by suppressing logical errors exponentially with code distance once physical error rates fall below a critical threshold. Here we demonstrate below-threshold operation of triangular color codes with distances d=3,5,d=3,5,d=3,5, and 777 on Quantinuum's Helios trapped-ion quantum processor. Leveraging both circuit- and hardware- level leakage reduction schemes, we achieve logical error rates as low as 5−2+4×10−65_{-2}^{+4}\times 10^{-6}5−2+4​×10−6, and demonstrate error suppression by over an order of magnitude, Λ=12−2+3Λ=12_{-2}^{+3}Λ=12−2+3​, with each successive increase in code distance. Moreover, we demonstrate below threshold scaling of error rates for Clifford two-qubit randomized benchmarking circuits when encoded in d=3,5d=3,5d=3,5 color codes, achieving logical error rate of 7−3+3×10−57^{+3}_{-3}\times 10^{-5}7−3+3​×10−5 per logical two-qubit Clifford at distance 555 with a suppression factor of Λ=9−3+8Λ=9_{-3}^{+8}Λ=9−3+8​. We compare logical performance for existing near-optimal algorithmic decoders, and both convolutional neural network and transformer-based neural network decoders capable of real-time decoding an order of magnitude faster than the syndrome extraction rate. These results approach the logical error rates required for megaquop-scale quantum computation and indicate that scaled trapped-ion processors could reach application-relevant performance with substantially smaller code blocks than indicated by previous results in other qubit modalities.
Current quantum processors are fragile, noisy and fairly limited in both quantity and quality with tens of qubits and physical error rates of around 10^-3. To realize practical quantum applications, however, error rates need to be below 10^-15 across millions of qubits. To bridge this gap and fully harness the potential of quantum computers, quantum error correction (QEC) is essential. QEC codes are designed to protect quantum information by redundantly encoding it onto multiple physical qubits. This encoding allows for the detection and correction of local errors affecting individual qubits, e.g., through stabilizer measurements. Importantly, if the physical error rates are below a specific threshold, QEC codes can exponentially suppress logical error rates by increasing the number of physical qubits involved. This is essential for achieving fault-tolerant computations, which are key to unlocking the full potential of quantum computers. The work presented in this thesis focuses on the implementation and optimization of small-scale QEC experiments using the surface code and flux-tunable superconducting qubits (Transmons). It addresses several key challenges: enhancing two-qubit gate fidelity in Surface-4 (Chapter 2), implementing an error-detection code with Surface-7 (Chapter 3), automating the calibration and benchmarking of the building blocks in Surface-17 (Chapter 4), reducing leakage into higher excited states with leakage reduction units (Chapter 5), assessing and enhancing the performance of logical qubits (Chapters 7 and 8).