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Noise Mitigation Through Design and Optimization of Parametric Quantum Channels

LEONE, PIETRO

Published Oct 15, 2025• 0 citations
OpenAlex

Abstract

The primary aim of the thesis is to introduce and investigate an original protocol for the design and the optimization of parameterized noisy quantum channels, with the goal of mitigating hardware-induced noise. Significant attention is also devoted to the design of noise models, which are essential for emulation purposes. The protocol begins with the derivation of a noise model for a hardware gate, represented as a quantum channel, that can be simulated classically. This task is achieved through process tomography, a procedure that enables the characterization of the channel. It should be noted that such simulation is feasible on classical computers, since the optimization task concerns low-dimensional gates typically acting on 2–3 qubits. The noisy channel is then engineered by embedding it into a probabilistic ensemble of circuits, in which additional single-qubit parameterized gates — assumed to be noiseless — are introduced. Through this procedure, the noisy channel becomes parameterized and can be optimized according to an appropriate metric. Following a worst-case, agnostic perspective, we choose the diamond distance between the noisy channel and the target unitary channel as the cost function. This metric is generally considered the most suitable for distinguishing quantum channels. The resulting optimal ensemble of circuits can be implemented on real hardware under fixed calibration conditions, yielding a channel that approximates the target more closely than the original noisy channel. This approach can be interpreted as a noise mitigation strategy based on pre-processing design and optimization: rather than correcting errors after the computation, less noisy channels are employed during the computation itself. In this context, the protocol — within the noise-aware variational quantum compiling framework — shares with the randomized compiling the principle of circuit dressing to tailor noise during execution. The methodology is validated on two toy models of the single-qubit identity with amplitude damping noise, combining both analytical and numerical approaches. The analysis highlights the role of convexity in the space of quantum channels, with explicit demonstrations of optimal convex combinations and connections to encoding-decoding and dynamical decoupling strategies. The analysis of these simple models is intended as a proof-of-principle of the protocol in a controlled and well-characterized environment. In addition, this thesis introduces the design of random noise models that are constrained to maintain a fixed diamond distance from a target quantum channel. The controlled addition of random noise to a unitary channel represents a significant and — to our knowledge — previously unexplored approach within noise modeling. Indeed, in principle, the currently available built-in noise models may limit the expressivity of the emulation. The task was achieved by enriching the noise spectrum through the addition of random Kraus operators and small systematic rotations. To assess the effects of hardware-induced noise, we proposed an experimental design aimed at simulating the time evolution of a triangular Ising model in a transverse field. Our approach employs Trotterization, adapted to the topology and connectivity of a certain quantum processing unit (QPU) profile. Building on the noisy native gates of the QPU profile, we propose the emulation, engineering and optimization of a noisy CZ gate, subsequently employed within sequences of non-native gates. Using the designed noise models, we perform several emulations aimed at evaluating the effectiveness of the protocol in the presence of progressively dominant systematic rotations, and at comparing it with Pauli twirling, a technique of randomized compiling.

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The primary aim of the thesis is to introduce and investigate an original protocol for the design and the optimization of parameterized noisy quantum channels, with the goal of mitigating hardware-induced noise. Significant attention is also devoted to the design of noise models, which are essential for emulation purposes. The protocol begins with the derivation of a noise model for a hardware gate, represented as a quantum channel, that can be simulated classically. This task is achieved through process tomography, a procedure that enables the characterization of the channel. It should be noted that such simulation is feasible on classical computers, since the optimization task concerns low-dimensional gates typically acting on 2–3 qubits. The noisy channel is then engineered by embedding it into a probabilistic ensemble of circuits, in which additional single-qubit parameterized gates — assumed to be noiseless — are introduced. Through this procedure, the noisy channel becomes parameterized and can be optimized according to an appropriate metric. Following a worst-case, agnostic perspective, we choose the diamond distance between the noisy channel and the target unitary channel as the cost function. This metric is generally considered the most suitable for distinguishing quantum channels. The resulting optimal ensemble of circuits can be implemented on real hardware under fixed calibration conditions, yielding a channel that approximates the target more closely than the original noisy channel. This approach can be interpreted as a noise mitigation strategy based on pre-processing design and optimization: rather than correcting errors after the computation, less noisy channels are employed during the computation itself. In this context, the protocol — within the noise-aware variational quantum compiling framework — shares with the randomized compiling the principle of circuit dressing to tailor noise during execution. The methodology is validated on two toy models of the single-qubit identity with amplitude damping noise, combining both analytical and numerical approaches. The analysis highlights the role of convexity in the space of quantum channels, with explicit demonstrations of optimal convex combinations and connections to encoding-decoding and dynamical decoupling strategies. The analysis of these simple models is intended as a proof-of-principle of the protocol in a controlled and well-characterized environment. In addition, this thesis introduces the design of random noise models that are constrained to maintain a fixed diamond distance from a target quantum channel. The controlled addition of random noise to a unitary channel represents a significant and — to our knowledge — previously unexplored approach within noise modeling. Indeed, in principle, the currently available built-in noise models may limit the expressivity of the emulation. The task was achieved by enriching the noise spectrum through the addition of random Kraus operators and small systematic rotations. To assess the effects of hardware-induced noise, we proposed an experimental design aimed at simulating the time evolution of a triangular Ising model in a transverse field. Our approach employs Trotterization, adapted to the topology and connectivity of a certain quantum processing unit (QPU) profile. Building on the noisy native gates of the QPU profile, we propose the emulation, engineering and optimization of a noisy CZ gate, subsequently employed within sequences of non-native gates. Using the designed noise models, we perform several emulations aimed at evaluating the effectiveness of the protocol in the presence of progressively dominant systematic rotations, and at comparing it with Pauli twirling, a technique of randomized compiling.
The rapid advancement of Noisy Intermediate-Scale Quantum (NISQ) devices has driven the need for efficient design automation tools that can translate complex engineering models into executable quantum circuits. This study explores the development of automated quantum circuit design frameworks focused on gate optimization and noise-aware compilation, enabling practical quantum computation for engineering applications such as optimization, simulation, and control systems. Traditional circuit design methods often fail to account for hardware constraints, decoherence, and gate infidelity, which significantly affect computational accuracy on NISQ devices. To address these challenges, this research introduces a hybrid automation approach combining quantum transpilation, variational circuit pruning, and error-aware synthesis algorithms to enhance circuit reliability and scalability. The framework integrates quantum-classical co-design principles to optimize both logical and physical circuit layers, leveraging hardware-specific calibration data to adapt compilation strategies dynamically. Through simulations and benchmark analysis, the proposed system demonstrates significant improvements in quantum resource utilization, error mitigation, and gate depth reduction compared to conventional compilation methods. This work underscores the growing importance of design automation in quantum engineering, where algorithmic efficiency must be harmonized with physical constraints to realize functional and scalable quantum workflows. By establishing a methodology for gate-level optimization and noise-adaptive design, the study contributes to bridging the gap between theoretical quantum algorithms and real-world engineering implementations within the NISQ computing era.
Quantum circuit optimization - the process of transforming a quantum circuit into an equivalent one with reduced time and space requirements - is crucial for maximizing the utility of current and near-future quantum devices. While most automated optimization techniques focus on transforming circuits into equivalent ones that implement the same unitary, we show that substantial new opportunities for resource reduction can be achieved by (1) allowing approximate local transformations and (2) employing mixed quantum channels to approximate pure circuits. Our novel automated protocol for approximate circuit rewriting is a refined evolution of automated optimization techniques based on the ZX-calculus, where we add a greedy strategy that selectively replaces ZX-diagrams with small phase angles with stochastic mixtures of the identity and carefully chosen over-rotations, which are designed to reduce the overall gate count in expectation while staying within a strict error budget. This approach yields modest two-qubit gate count reduction in random quantum circuits, and achieves a substantial reduction in structured circuits such as the quantum Fourier transform. Fundamentally, our protocol converts experimental noise due to gate applications into deliberately engineered random noise, outperforming many other approximation methods on average. These results highlight the potential of mixed-channel approximations to enhance future quantum circuit performance, suggesting new directions for resource-aware automated quantum compilation beyond pure unitary channels.
Non-unitary protocols are already at the base of many hybrid quantum computing applications, especially in the noisy intermediate-scale quantum (NISQ) era where quantum errors typically affect the unitary evolution. However, while the framework for Parameterized Quantum Circuits is widely developed, especially for applications where the parameters are optimized towards a set goal, we find there are still interesting opportunities in defining a unified framework also for non-unitary protocols in the form of Parameterized Quantum Channels as a computing resource. We first discuss the general parameterization strategies for controlling quantum channels and their practical realizations. Then we describe a simple example of application in the context of error mitigation, where the control parameters for the quantum channels are optimized in the presence of noise, in order to maximize channel fidelity with respect to a given target channel.
Maximizing the computational utility of near-term quantum processors requires predictive noise models that inform robust, noise-aware compilation and error mitigation. Conventional models often fail to capture the complex error dynamics of real hardware or require prohibitive characterization overhead. We introduce a data-efficient framework that first constructs a physically motivated, parameterized noise model, and subsequently employs machine-learning-driven Bayesian optimization to identify its parameters. Our approach circumvents costly characterization protocols by estimating algorithm- and hardware-specific error parameters directly from readily available experimental data derived from existing application and benchmark circuit executions. The generality and robustness of the framework are demonstrated across diverse algorithms and superconducting devices, yielding high-fidelity predictions by estimating an independent parameter set tailored to each specific algorithm-hardware context. Crucially, we show that a model calibrated exclusively on small-scale circuits accurately predicts the behavior of larger validation circuits. Our data-efficient approach achieves up to a 65% improvement in model fidelity quantified by the Hellinger distance between predicted and experimental circuit output distributions, compared to standard noise models derived from device properties. This work establishes a practical paradigm for application-aware noise characterization, enabling compilation and error-mitigation strategies tailored to the specific interplay between quantum algorithms and device-specific noise dynamics.
Using near-term quantum computers to achieve a quantum advantage requires efficient strategies to improve the performance of the noisy quantum devices presently available. We develop and experimentally validate two efficient error mitigation protocols named ``Noiseless Output Extrapolation" and ``Pauli Error Cancellation" that can drastically enhance the performance of quantum circuits composed of noisy cycles of gates. By combining popular mitigation strategies such as probabilistic error cancellation and noise amplification with efficient noise reconstruction methods, our protocols can mitigate a wide range of noise processes that do not satisfy the assumptions underlying existing mitigation protocols, including non-local and gate-dependent processes. We test our protocols on a four-qubit superconducting processor at the Advanced Quantum Testbed. We observe significant improvements in the performance of both structured and random circuits, with up to 86% improvement in variation distance over the unmitigated outputs. Our experiments demonstrate the effectiveness of our protocols, as well as their practicality for current hardware platforms.
Quantum errors in noisy environments remain a major obstacle to advancing quantum information technology. In this work, we expand a recently developed geometric framework, originally utilized for analyzing noise accumulation and creating dynamical error-correcting gates at the control pulse level, to now study noise dynamics at the quantum circuit level. Through a geometric perspective, we demonstrate how circuit noise robustness can be enhanced using twirling techniques. Additionally, we show that circuits modified by random twirling correspond to random walk trajectories in this geometric framework, and provide a fresh perspective on randomized compiling by analytically deriving the perturbative expression for the resultant Pauli noise channel. We also illustrate that combining robustness optimization strategies at both the control pulse and circuit levels can significantly boost overall circuit fidelity even further through numerical examples. This research illuminates pathways to achieving noise-resistant quantum control beyond mere optimization of control pulses.