We report the first real-hardware implementation and verification of Dual Boundary Condition Inference (DBCI) on IBM Quantum systems. This work validates the predicted size-dependent transition in DBCI's information flow dynamics. Leveraging the ibm_brisbane (127-qubit) and ibm_fez processors, we conducted a systematic analysis using random-circuit sampling across an unprecedented range of 9–100 qubits. The experimental results established a robust, reproducible entropy-collapse signature characterized by three distinct regimes: Amplification (Small Circuits, < 13 qubits): Demonstrated significant multi-bit coherence gains ( bits). Saturation (Large Circuits, qubits): Consistently converged to the theoretical algebraic limit, bits. Bistability (Intermediate Circuits): A sharp crossover regime between the two limits. Matched noiseless simulations confirmed that this entire three-regime structure—amplification, bistability, and saturation—arises solely from the intrinsic algebraic properties of the DBCI update kernel, rather than from hardware noise. High-precision verification showed that the marginal hardware–simulator offset was statistically indistinguishable from zero. This evidence suggests that the saturation represents a hardware-stable invariance condition inherent to dual-boundary inference, indicating a deterministic crossover between finite-size coherence effects and fundamental boundary-limited information flow in quantum systems.
We report the first real-hardware implementation and verification of Dual Boundary Condition Inference (DBCI) on IBM Quantum systems. This work validates the predicted size-dependent transition in DBCI's information flow dynamics. Leveraging the ibm_brisbane (127-qubit) and ibm_fez processors, we conducted a systematic analysis using random-circuit sampling across an unprecedented range of 9–100 qubits. The experimental results established a robust, reproducible entropy-collapse signature characterized by three distinct regimes: Amplification (Small Circuits, < 13 qubits): Demonstrated significant multi-bit coherence gains ( bits). Saturation (Large Circuits, qubits): Consistently converged to the theoretical algebraic limit, bits. Bistability (Intermediate Circuits): A sharp crossover regime between the two limits. Matched noiseless simulations confirmed that this entire three-regime structure—amplification, bistability, and saturation—arises solely from the intrinsic algebraic properties of the DBCI update kernel, rather than from hardware noise. High-precision verification showed that the marginal hardware–simulator offset was statistically indistinguishable from zero. This evidence suggests that the saturation represents a hardware-stable invariance condition inherent to dual-boundary inference, indicating a deterministic crossover between finite-size coherence effects and fundamental boundary-limited information flow in quantum systems.
We investigate whether a training-free thermodynamic stability metric Φ = I × ρ - α × S, computed from IBM Quantum calibration data before circuit execution, can serve as a routing signal for allocating computation between quantum hardware and classical simulation in the tested setting. Across 23 tests on real IBM Quantum hardware, we validate a Φ-based routing framework and show in direct crossover tests that LOW-Φ quantum execution can be worse than exact classical simulation for the tested classically tractable circuits: in the primary crossover test, classical simulation achieved 0.00% error while LOW-Φ quantum execution produced 8.23% error on the same circuit. Under a strict methodology with verified physical qubit binding and decisive ground truth, HIGH-Φ versus LOW-Φ error ratios ranged from 2.90x (QPE) to 30.47x (Bernstein-Vazirani) across 7 tested algorithms. The strict seven-algorithm tests constitute the primary evidence layer, while the broader 23-test suite provides supporting boundary conditions on size, depth, and reproducibility. Circuit size and depth impose additional routing boundaries: in the tested conditions, LOW-Φ execution at 15 qubits produced 94.85% error and execution at circuit depth 103 produced 67.29% error, both transitions into regimes where classical fallback was more reliable. These results support a routing decision framework in which minimum Φ across circuit qubits determines whether to execute on quantum hardware or fall back to classical simulation, with hybrid strategies retained as a natural extension. The methods described in this paper are the subject of U.S. Provisional Patent Application No. 63/956,752 (filed January 9, 2026). No license to implement or commercialize the described methods is granted by this publication. All rights reserved.
A purely epistemic interpretation of wavefunction collapse predicts that hardware measurement statistics remain bounded by ideal quantum evolution and calibrated device noise models. We test this prediction using a three-reference validation framework comparing hardware measurements against both ideal unitary evolution and noise-modeled simulations across six quantum computing platforms. In multiple experimental topologies, hardware results consistently fall outside both reference bounds by statistically significant margins and exhibit reproducible, topology-dependent deviation patterns. These deviations appear both at qubits in the collapsed branch and nonlocally across the entangled partner branch that received no collapse operation, with correlated topology-dependent deviation patterns indicating propagation through the W-state entanglement structure. The observed behavior is inconsistent with purely epistemic collapse models and suggests the presence of additional physical dynamics not captured by standard descriptions of measurement.
Qubit layout selection determining which physical qubits a logical circuit occupies on a superconducting processor is fundamentally a noise-field sampling problem. On IBM Heron r1 and Heron r2 devices, two-qubit gate error varies by nearly one order of magnitude (7– $9\times $ ) across qubit pairs on the same chip, causing measured fidelity differences up to 0.903 from layout choice alone. We introduce the Gate Noise Sensitivity Index (GNSI), a calibration-weighted linear combination of per-qubit readout error and per-edge two-qubit gate error, derived analytically as a first-order approximation of circuit fidelity under independent, heterogeneous noise channels. For 12 backend–circuit combinations on three IBM processors (133-qubit Heron r1 and 156-qubit Heron r2), GNSI scores are computed for the full pool of 1,320 computationally enumerated candidate layouts; the top-ranked (GNSI-BEST) and bottom-ranked (GNSI-WORST) layouts are then executed on hardware. GNSI-BEST ranks first by score in all 12 instances (Hit@1 = 100% within the enumerated candidate pool) and consistently achieves higher measured fidelity than GNSI-WORST, with Spearman rank correlation ρ=0.926±0.016 and statistically significant fidelity separation in 9 of 12 paired tests. Initial hardware comparisons on ibm_fez ( n=5 ) show GNSI-BEST matching or exceeding SABRE-selected fidelity. We further identify a depth-dependent regime transition: gate-error heterogeneity appears to govern ranking in shallow circuits (depth ≤15 ), while qubit-specific T1 variation may dominate for deeper circuits (depth ≥20 ). The analytic regime boundary d∗(b) , computable from calibration data alone, shows agreement within ±2 depth layers across all three backends in initial comparisons; GNSI-Extended incorporating the decoherence term receives an initial hardware comparison on two circuits, with full validation left to future work. These results suggest that layout-dependent fidelity variation may be governed by a calibration-predictable noise field, with direct implications for compiler design and noise-adaptive quantum circuit execution.
The practical utility of Noisy Intermediate-Scale Quantum (NISQ) processors depends critically on their performance under demanding computational loads. We investigated the impact of circuit depth on the 127-qubit superconducting processor ibm_brisbane by executing stress-test circuits utilizing all available qubits. These circuits consisted of repeated layers combining random single-qubit rotations and linear chains of Controlled-Z entangling gates. We systematically increased the ideal circuit depth from 1 up to 30 layers, resulting in transpiled circuits ranging from approximately 550 to over 15,000 gates (optimization level 2). Using the qiskit-ibm-runtime Sampler primitive with 4096 shots and default error mitigation, we successfully obtained results for ideal depths up to 22 (transpiled depth ~11.7k gates), beyond which platform usage limits prevented execution. Our central finding is the immediate onset of noise saturation: the output distribution reached maximum sample entropy (12.0 bits) and exhibited near-zero average single-qubit Z magnetization even at the shallowest depth tested (ideal depth 1, transpiled depth ~550). These noise-dominated characteristics persisted despite significant increases in transpiled circuit depth. This demonstrates that for these specific full-width, complex random circuits, noise overwhelms the computation almost instantaneously on this device under default settings, highlighting the profound challenge of achieving computational fidelity for deep, wide algorithms in the NISQ era without advanced error handling.
Random unitaries scramble quantum information into highly nonlocal degrees of freedom, thereby providing protection from local noise. However, as demonstrated by Turkeshi and Sierant (Phys. Rev. Lett. 132, 140401, 2024 and arXiv:2603.00235), this protection may fail once local noise grows sufficiently strong. These works describe a phase transition in a noisy random encoding-decoding circuit model between an error-protecting phase, in which encoded information is recoverable, and an error-vulnerable phase, in which encoded information is lost, with the transition occurring at a critical coherent noise angle αc≈1.14. Here, we present the first experimental observation of this transition, conducted on IBM's ibm_pittsburgh Heron r3 device for system sizes of up to N=26 qubits. We detect this transition via three order parameters: fidelity, Rényi-2 entanglement entropy, and stabilizer Rényi-2 entropy. For the latter two, we employ randomized measurement protocols to construct estimators, and for all three, we rely on zero-noise extrapolation and M3 SPAM error mitigation. We then jointly model the finite-size scaling collapse across all three order parameters with a Gaussian process regression, yielding a critical angle αc≈1.01, well below the theoretical value. Inputting noiseless simulated data into the same model yields αc≈1.05, implying that the discrepancy between experiment and theory is due to our encoding circuits, which are not deep enough to be truly Haar-random. Finally, we observe that the same model cannot adequately identify critical behavior in unmitigated, raw experimental data. This indicates that error mitigation techniques are crucial for detecting the transition on hardware.
The practical utility of Noisy Intermediate-Scale Quantum (NISQ) processors depends critically on their performance under demanding computational loads. We investigated the impact of circuit depth on the 127-qubit superconducting processor ibm_brisbane by executing stress-test circuits utilizing all available qubits. These circuits consisted of repeated layers combining random single-qubit rotations and linear chains of Controlled-Z entangling gates. We systematically increased the ideal circuit depth from 1 up to 30 layers, resulting in transpiled circuits ranging from approximately 550 to over 15,000 gates (optimization level 2). Using the qiskit-ibm-runtime Sampler primitive with 4096 shots and default error mitigation, we successfully obtained results for ideal depths up to 22 (transpiled depth ~11.7k gates), beyond which platform usage limits prevented execution. Our central finding is the immediate onset of noise saturation: the output distribution reached maximum sample entropy (12.0 bits) and exhibited near-zero average single-qubit Z magnetization even at the shallowest depth tested (ideal depth 1, transpiled depth ~550). These noise-dominated characteristics persisted despite significant increases in transpiled circuit depth. This demonstrates that for these specific full-width, complex random circuits, noise overwhelms the computation almost instantaneously on this device under default settings, highlighting the profound challenge of achieving computational fidelity for deep, wide algorithms in the NISQ era without advanced error handling.