Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE International Conference on Quantum Computing and Engineering (QCE)

A Real-Time Low-Latency Quantum Error Correction Stack: Deltaflow and Deltakit

Nick P. Johnson, Abe Asfaw, Guen Prawiroatmodjo, Tom Hartley, Stas Protasov, Chidi Nnadi, Amirreza Safehian, Jatin Lal, Charn Sangvirojkul, Gianluca Aiello, Matthew J. A. Ruszala, Liz Durst

Published Aug 30, 2025• 1 citation
Publisher

Abstract

Quantum computing researchers in academia and industry have demonstrated increasingly sophisticated experiments that incorporate quantum error correction (QEC) to improve the reliability of logical computations [1]–[4]. Error correction preserves quantum information by encoding logical qubits which are subject to lower error rates than their constituent physical qubits. The degree of error suppression depends on the choice of error-correcting code and distance, the underlying physical error rate, and the accuracy of the decoder. It is widely regarded that QEC is necessary to reach the low error rates required to perform reliable quantum algorithms on large-scale quantum devices. In this poster, we describe our real-time, lowlatency QEC accelerator, Deltaflow 2, which is designed as a modular sub-system that connects to a quantum control system using a universal interface. Deltaflow 2 contains a high-accuracy decoder, and enables streaming quantum memory experiments with wide applicability to a range of different qubit platforms. In addition, we address a gap in the current landscape of opensource quantum software, demonstrating tools for compilation, simulation and decoding of error-corrected quantum circuits using our python library, Deltakit. Together, these tools deliver a comprehensive QEC stack for implementing error correction on quantum hardware.

DOI
10.1109/qce65121.2025.10454

Related papers

Real-Time Quantum Error Correction System Stack: Architecture, Algorithms, and Engineering Practice

Yaojian Chen, Chun-Yang Luan, Peilin Zheng +7 more

Quantum error correction (QEC) is transitioning from physical feasibility demonstrations to systems engineering challenges. Google has achieved below-threshold performance on distance-5/7 surface codes, while Riverlane and Rigetti have demonstrated hardware-integrated low-latency feedback loops. These milestones indicate that the core challenge of real-time decoding has shifted from algorithmic capability to system-level engineering. However, a substantial engineering gap remains between laboratory demonstrations and scalable fault-tolerant quantum computing (FTQC). This white paper addresses three questions: (1) Where are the real bottlenecks in real-time QEC: beyond average decoder speed, the constraints lie in QEC round time, tail latency, and end-to-end data path coordination; (2) How mature are mainstream decoder algorithms: we benchmark the major decoders for both surface codes and quantum low-density parity-check (qLDPC) codes, evaluating their real-time readiness; (3) What system stack do we propose: a six-layer reference architecture from syndrome acquisition to logical operations, with interface definitions and latency budget models. Our results quantify the gap between current decoder performance and real-time requirements, and identify the architectural choices needed to close it.

quant-pharXiv:2605.30765•Jun 1, 2026•0 citations

Low Latency GNN Accelerator for Quantum Error Correction

Alessio Cicero, Luigi Altamura, Moritz Lange +2 more

Quantum computers can solve selected problems more efficiently than classical computers, but current devices are limited by high physical error rates. Quantum Error Correction (QEC) mitigates this by encoding many physical qubits into a logical qubit, with the surface code among the most widely studied approaches. Since syndrome measurements are produced continuously, the decoder must process them fast enough to avoid becoming a system bottleneck, making real-time decoding essential for fault-tolerant quantum computing. While most state-of-the-art real-time decoders rely on Minimum-Weight Perfect Matching (MWPM), we instead use a high-accuracy Graph Neural Network (GNN) that trades higher computational cost for lower logical error rates. To make this GNN practical for real-time decoding, we apply algorithm-hardware co-design. We reduce complexity through hardware-guided pruning and retraining, producing two hardware-friendly models that reduce parameter count by $3.1\times$ and $6.5\times$. These target, respectively, an average decoding latency of one syndrome cycle and a worst-case latency within one syndrome cycle. We further reduce hardware cost using input-graph filtering and post-training quantization. Based on these optimized models, we propose an FPGA-based architecture for low-latency inference and real-time decoding. Evaluated on surface codes up to distance 7 under circuit-level noise at physical error rate $p=10^{-3}$, our decoder outperforms MWPM in decoding accuracy for both average-latency and max-latency settings. It reduces logical error rate by 40% at $1μs$ average latency, and by 13% under a strict $1μs$ deadline.

quant-pharXiv:2603.22149•Mar 24, 2026•0 citations

A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency

Junyi Liu, Yi Lee, Yilun Xu +2 more

Quantum error correction (QEC) is essential for realizing large-scale, fault-tolerant quantum computation, yet its practical implementation remains a major engineering challenge. In particular, QEC demands precise real-time control of a large number of qubits and low-latency, high-throughput and accurate decoding of error syndromes. While most prior work has focused primarily on decoder design, the overall performance of any QEC system depends critically on all its subsystems including control, communication, and decoding, as well as their integration. To address this challenge, we present an open-source, fully integrated QEC system built on RISC-Q, a generator for RISC-V-based quantum control architectures. Implemented on RFSoC FPGAs, our system prototype integrates real-time qubit control, a scalable distributed multi-board architecture, and the state-of-the-art hardware QEC decoder within a low-latency, high-throughput decoding pipeline, forming a complete hardware platform ready for deployment with superconducting qubits. Experimental evaluation on a three-board prototype based on AMD ZCU216 RFSoCs demonstrates an end-to-end QEC decoding-feedback latency of 446 ns for a distance-3 surface code, including syndrome aggregation, network communication, syndrome decoding, and error distribution. Extrapolating from measured subsystem performance and state-of-the-art decoder benchmarks, the architecture can achieve sub-microsecond decoding-feedback latency up to a distance-21 surface code ($\sim$881 physical qubits) when scaled to larger hardware configurations.

quant-pharXiv:2603.16203•Mar 18, 2026•0 citations

Demonstrating real-time and low-latency quantum error correction with superconducting qubits

Laura Caune, Luka Skorić, Nick S. Blunt +22 more

Quantum error correction will be essential for quantum computers to realise their full potential. As quantum computers advance towards demonstrating a universal fault-tolerant logical gate set, implementing scalable and low-latency real-time decoding will be crucial to avoid an exponential slowdown and maintain a fast logical clock rate. Here, we demonstrate low-latency feedback with a scalable FPGA decoder integrated into the control system of a superconducting quantum processor. We perform an 8-qubit stability experiment with up to 25 decoding rounds and a sub-microsecond mean decoding time per round, providing strong evidence that the backlog problem will be avoided when the decoder is operated as a streaming decoder on a superconducting hardware with the strictest speed requirements. We observe logical error suppression as the number of decoding rounds is increased. We also implement and time a fast-feedback experiment demonstrating a decoding response time of 9.6 μs for a total of 9 measurement rounds.

arXiv:2410.05202•Nature Communications•Jun 1, 2026•12 citations

LILLIPUT: a lightweight low-latency lookup-table decoder for near-term Quantum error correction

Poulami Das, Aditya Locharla, Cody Jones

The error rates of quantum devices are orders of magnitude higher than what is needed to run most quantum applications. To close this gap, Quantum Error Correction (QEC) encodes logical qubits and distributes information using several physical qubits. By periodically executing a syndrome extraction circuit on the logical qubits, information about errors (called syndrome) is extracted while running programs. A decoder uses these syndromes to identify and correct errors in real time, which is necessary to prevent accumulation of errors. Unfortunately, software decoders are slow and hardware decoders are fast but less accurate. Thus, almost all QEC studies so far have relied on offline decoding.

International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)•Feb 22, 2022•52 citations

Analyzing Decoders for Quantum Error Correction

Abtin Molavi, Feras Saad, Aws Albarghouthi

Quantum error correction (QEC) enables reliable computation on noisy hardware by encoding logical information across many physical qubits and periodically measuring parities to detect errors. A decoder is the classical algorithm that uses these measurements to infer which error most likely occurred, so that the system can correct it. The decoder's accuracy-how rarely it makes the wrong guess-directly determines the scale of quantum computation that can be reliably executed. With a wealth of competing decoding algorithms, a QEC system designer needs reliable methods to evaluate them. Today, the dominant approach is to evaluate decoders using Monte Carlo simulation. However, simulation has several drawbacks such as requiring many samples to produce low variance estimates. In this work, we develop a new systematic analysis for evaluating decoders. We introduce a novel formal semantics of a core language for QEC programs that captures the de facto standard Stim circuit format, providing a principled theoretical foundation for the emerging space of fault-tolerant quantum systems design. Given a QEC program and a decoder, our verifier can quantify both the decoder accuracy and the decoder robustness to drift in physical error rate. Our approach has two key components: (i) a structured search over the space of possible errors; and (ii) a constrained polynomial optimization kernel. A thorough empirical evaluation of our approach suggests that it can outperform simulation, especially in low error rate regimes, and that it can be deployed to quantify decoder robustness over an interval of physical error rates.

cs.PLCross-listedarXiv:2603.20127•Mar 23, 2026•0 citations
Quantum computing researchers in academia and industry have demonstrated increasingly sophisticated experiments that incorporate quantum error correction (QEC) to improve the reliability of logical computations [1]–[4]. Error correction preserves quantum information by encoding logical qubits which are subject to lower error rates than their constituent physical qubits. The degree of error suppression depends on the choice of error-correcting code and distance, the underlying physical error rate, and the accuracy of the decoder. It is widely regarded that QEC is necessary to reach the low error rates required to perform reliable quantum algorithms on large-scale quantum devices. In this poster, we describe our real-time, lowlatency QEC accelerator, Deltaflow 2, which is designed as a modular sub-system that connects to a quantum control system using a universal interface. Deltaflow 2 contains a high-accuracy decoder, and enables streaming quantum memory experiments with wide applicability to a range of different qubit platforms. In addition, we address a gap in the current landscape of opensource quantum software, demonstrating tools for compilation, simulation and decoding of error-corrected quantum circuits using our python library, Deltakit. Together, these tools deliver a comprehensive QEC stack for implementing error correction on quantum hardware.
Quantum error correction (QEC) is transitioning from physical feasibility demonstrations to systems engineering challenges. Google has achieved below-threshold performance on distance-5/7 surface codes, while Riverlane and Rigetti have demonstrated hardware-integrated low-latency feedback loops. These milestones indicate that the core challenge of real-time decoding has shifted from algorithmic capability to system-level engineering. However, a substantial engineering gap remains between laboratory demonstrations and scalable fault-tolerant quantum computing (FTQC). This white paper addresses three questions: (1) Where are the real bottlenecks in real-time QEC: beyond average decoder speed, the constraints lie in QEC round time, tail latency, and end-to-end data path coordination; (2) How mature are mainstream decoder algorithms: we benchmark the major decoders for both surface codes and quantum low-density parity-check (qLDPC) codes, evaluating their real-time readiness; (3) What system stack do we propose: a six-layer reference architecture from syndrome acquisition to logical operations, with interface definitions and latency budget models. Our results quantify the gap between current decoder performance and real-time requirements, and identify the architectural choices needed to close it.
Quantum computers can solve selected problems more efficiently than classical computers, but current devices are limited by high physical error rates. Quantum Error Correction (QEC) mitigates this by encoding many physical qubits into a logical qubit, with the surface code among the most widely studied approaches. Since syndrome measurements are produced continuously, the decoder must process them fast enough to avoid becoming a system bottleneck, making real-time decoding essential for fault-tolerant quantum computing. While most state-of-the-art real-time decoders rely on Minimum-Weight Perfect Matching (MWPM), we instead use a high-accuracy Graph Neural Network (GNN) that trades higher computational cost for lower logical error rates. To make this GNN practical for real-time decoding, we apply algorithm-hardware co-design. We reduce complexity through hardware-guided pruning and retraining, producing two hardware-friendly models that reduce parameter count by 3.1×3.1\times3.1× and 6.5×6.5\times6.5×. These target, respectively, an average decoding latency of one syndrome cycle and a worst-case latency within one syndrome cycle. We further reduce hardware cost using input-graph filtering and post-training quantization. Based on these optimized models, we propose an FPGA-based architecture for low-latency inference and real-time decoding. Evaluated on surface codes up to distance 7 under circuit-level noise at physical error rate p=10−3p=10^{-3}p=10−3, our decoder outperforms MWPM in decoding accuracy for both average-latency and max-latency settings. It reduces logical error rate by 40% at 1μs1μs1μs average latency, and by 13% under a strict 1μs1μs1μs deadline.
Quantum error correction (QEC) is essential for realizing large-scale, fault-tolerant quantum computation, yet its practical implementation remains a major engineering challenge. In particular, QEC demands precise real-time control of a large number of qubits and low-latency, high-throughput and accurate decoding of error syndromes. While most prior work has focused primarily on decoder design, the overall performance of any QEC system depends critically on all its subsystems including control, communication, and decoding, as well as their integration. To address this challenge, we present an open-source, fully integrated QEC system built on RISC-Q, a generator for RISC-V-based quantum control architectures. Implemented on RFSoC FPGAs, our system prototype integrates real-time qubit control, a scalable distributed multi-board architecture, and the state-of-the-art hardware QEC decoder within a low-latency, high-throughput decoding pipeline, forming a complete hardware platform ready for deployment with superconducting qubits. Experimental evaluation on a three-board prototype based on AMD ZCU216 RFSoCs demonstrates an end-to-end QEC decoding-feedback latency of 446 ns for a distance-3 surface code, including syndrome aggregation, network communication, syndrome decoding, and error distribution. Extrapolating from measured subsystem performance and state-of-the-art decoder benchmarks, the architecture can achieve sub-microsecond decoding-feedback latency up to a distance-21 surface code ($\sim$881 physical qubits) when scaled to larger hardware configurations.
Quantum error correction will be essential for quantum computers to realise their full potential. As quantum computers advance towards demonstrating a universal fault-tolerant logical gate set, implementing scalable and low-latency real-time decoding will be crucial to avoid an exponential slowdown and maintain a fast logical clock rate. Here, we demonstrate low-latency feedback with a scalable FPGA decoder integrated into the control system of a superconducting quantum processor. We perform an 8-qubit stability experiment with up to 25 decoding rounds and a sub-microsecond mean decoding time per round, providing strong evidence that the backlog problem will be avoided when the decoder is operated as a streaming decoder on a superconducting hardware with the strictest speed requirements. We observe logical error suppression as the number of decoding rounds is increased. We also implement and time a fast-feedback experiment demonstrating a decoding response time of 9.6 μs for a total of 9 measurement rounds.
The error rates of quantum devices are orders of magnitude higher than what is needed to run most quantum applications. To close this gap, Quantum Error Correction (QEC) encodes logical qubits and distributes information using several physical qubits. By periodically executing a syndrome extraction circuit on the logical qubits, information about errors (called syndrome) is extracted while running programs. A decoder uses these syndromes to identify and correct errors in real time, which is necessary to prevent accumulation of errors. Unfortunately, software decoders are slow and hardware decoders are fast but less accurate. Thus, almost all QEC studies so far have relied on offline decoding.
Quantum error correction (QEC) enables reliable computation on noisy hardware by encoding logical information across many physical qubits and periodically measuring parities to detect errors. A decoder is the classical algorithm that uses these measurements to infer which error most likely occurred, so that the system can correct it. The decoder's accuracy-how rarely it makes the wrong guess-directly determines the scale of quantum computation that can be reliably executed. With a wealth of competing decoding algorithms, a QEC system designer needs reliable methods to evaluate them. Today, the dominant approach is to evaluate decoders using Monte Carlo simulation. However, simulation has several drawbacks such as requiring many samples to produce low variance estimates. In this work, we develop a new systematic analysis for evaluating decoders. We introduce a novel formal semantics of a core language for QEC programs that captures the de facto standard Stim circuit format, providing a principled theoretical foundation for the emerging space of fault-tolerant quantum systems design. Given a QEC program and a decoder, our verifier can quantify both the decoder accuracy and the decoder robustness to drift in physical error rate. Our approach has two key components: (i) a structured search over the space of possible errors; and (ii) a constrained polynomial optimization kernel. A thorough empirical evaluation of our approach suggests that it can outperform simulation, especially in low error rate regimes, and that it can be deployed to quantify decoder robustness over an interval of physical error rates.