Quantum computers are growing at a rapid pace. Trends show that the current decade could be the one in which quantum computers deliver commercial value. Today's quantum computers are overwhelmed by errors. To unlock their massive potential, a significant reduction in errors is required. Several qubit technologies are under research, e.g. superconducting, neutral atoms, trapped ions, photons and silicon. For useful quantum computing on these qubit technologies, Quantum Error Correction (QEC) turns unreliable physical qubits into useful logical qubits. QEC requires solving a real-time, large data volume decoding problem that determines the effect of physical noise on the computation carried out on logical qubits. The nature of the decoding problem depends on the qubit technology, choice of QEC code and mode of quantum computation. These are actively researched subjects in the quantum computing world. Hardware-based decoders that use Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuits (ASIC) technologies are the most promising solutions in terms of speed and scalability. However, the design methodology for these solutions typically suffers from long lead times and a lack of flexibility. We propose GridGenQ, a hardware design utility that automates part of the FPGA/ASIC design methodology for distributed QEC decoders. We show that with our novel solution, development time for such distributed hardware decoders can be reduced from several weeks to few minutes. This allows for fast prototyping of distributed decoder architectures to meet the requirements posed by a dynamic QEC landscape.
Quantum computers are growing at a rapid pace. Trends show that the current decade could be the one in which quantum computers deliver commercial value. Today's quantum computers are overwhelmed by errors. To unlock their massive potential, a significant reduction in errors is required. Several qubit technologies are under research, e.g. superconducting, neutral atoms, trapped ions, photons and silicon. For useful quantum computing on these qubit technologies, Quantum Error Correction (QEC) turns unreliable physical qubits into useful logical qubits. QEC requires solving a real-time, large data volume decoding problem that determines the effect of physical noise on the computation carried out on logical qubits. The nature of the decoding problem depends on the qubit technology, choice of QEC code and mode of quantum computation. These are actively researched subjects in the quantum computing world. Hardware-based decoders that use Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuits (ASIC) technologies are the most promising solutions in terms of speed and scalability. However, the design methodology for these solutions typically suffers from long lead times and a lack of flexibility. We propose GridGenQ, a hardware design utility that automates part of the FPGA/ASIC design methodology for distributed QEC decoders. We show that with our novel solution, development time for such distributed hardware decoders can be reduced from several weeks to few minutes. This allows for fast prototyping of distributed decoder architectures to meet the requirements posed by a dynamic QEC landscape.
Quantum computing is positioned to be a transformative technology to key areas of scientific interest such as quantum chemistry, material science, and cryptography. At a hardware level, recent years have seen broad progress in a variety of qubit modalities, however, error rates are still orders of magnitude higher than what is necessary for large-scale quantum programs. This gap in error rates motivates the use of quantum error correction (QEC) and the realization of fault-tolerant quantum computing (FTQC), yet today, although the theory of FTQC is promising, effectively connecting it to real devices poses significant challenges. In this dissertation we study opportunities for more efficient and scalable FTQC architectures through the co-design of quantum hardware and software. We first look at how unique hardware capabilities in quantum computers made from 2D arrays of optically trapped atoms can improve QEC performance. For computation, we study how longer-range interactions between atoms can enable a novel embedding of QEC blocks on physical qubits that improves logical-level connectivity. For memory, we study how mid-circuit movement of atoms can effectively implement higher encoding rate QEC codes, creating a qubit-efficient memory system. We next consider the performance impact of real-time classical systems in FTQC architectures, and explore the use of speculation to improve large-scale decoding systems. Finally, we study how software systems can be used to improve QEC designs. We consider the problem of QEC circuit optimization, and study an automated approach based on iterative optimization of performance-reducing subcircuits.
Quantum error correction (QEC) is essential for realizing large-scale, fault-tolerant quantum computation, yet its practical implementation remains a major engineering challenge. In particular, QEC demands precise real-time control of a large number of qubits and low-latency, high-throughput and accurate decoding of error syndromes. While most prior work has focused primarily on decoder design, the overall performance of any QEC system depends critically on all its subsystems including control, communication, and decoding, as well as their integration.
To address this challenge, we present an open-source, fully integrated QEC system built on RISC-Q, a generator for RISC-V-based quantum control architectures. Implemented on RFSoC FPGAs, our system prototype integrates real-time qubit control, a scalable distributed multi-board architecture, and the state-of-the-art hardware QEC decoder within a low-latency, high-throughput decoding pipeline, forming a complete hardware platform ready for deployment with superconducting qubits.
Experimental evaluation on a three-board prototype based on AMD ZCU216 RFSoCs demonstrates an end-to-end QEC decoding-feedback latency of 446 ns for a distance-3 surface code, including syndrome aggregation, network communication, syndrome decoding, and error distribution. Extrapolating from measured subsystem performance and state-of-the-art decoder benchmarks, the architecture can achieve sub-microsecond decoding-feedback latency up to a distance-21 surface code ($\sim$881 physical qubits) when scaled to larger hardware configurations.
Abstract Quantum computing is poised to solve practically useful problems which are computationally intractable for classical supercomputers. However, the current generation of quantum computers are limited by errors that may only partially be mitigated by developing higher-quality qubits. Quantum error correction (QEC) will thus be necessary to ensure fault tolerance. QEC protects the logical information by cyclically measuring syndrome information about the errors. An essential part of QEC is the decoder, which uses the syndrome to compute the likely effect of the errors on the logical degrees of freedom and provide a tentative correction. The decoder must be accurate, fast enough to keep pace with the QEC cycle (e.g. on a microsecond timescale for superconducting qubits) and with hard real-time system integration to support logical operations. As such, real-time decoding is essential to realize fault-tolerant quantum computing and to achieve quantum advantage. In this work, we highlight some of the key challenges facing the implementation of real-time decoders while providing a succinct summary of the progress to-date. Furthermore, we lay out our perspective for the future development and provide a possible roadmap for the field of real-time decoding in the next few years. As the quantum hardware is anticipated to scale up, this perspective article will provide a guidance for researchers, focusing on the most pressing issues in real-time decoding and facilitating the development of solutions across quantum, nano and computer science.
Quantum computing represents an exciting computing paradigm that promises to solve problems untractable for a classical computer. The main limiting factor for quantum devices is the noise impacting qubits, which hinders the superpolynomial speedup promise. Thus, although Quantum Error Correction (QEC) mechanisms are paramount, QEC demands high speed and low latency to scale quantum computations to real-life-sized problems. Within this context, hardware accelerators, such as Field Programmable Gate Arrays (FPGAs), represent a valuable approach to fulfilling QEC requirements. Nevertheless, the literature falls short in proposing solutions targeting the toric code, a type of quantum Low-Density Parity Check code capable of encoding two logical qubits, thus requiring fewer physical qubits. This manuscript presents QUEKUF , an FPGA-based QEC dataflow architecture dealing with the toric code. QUEKUF disposes of parallel processing units to spatially parallelize QEC, which a centralized controller orchestrates for data movement and operation decisions. We also provide a latency-oriented resource optimization model to identify the best theoretical configuration of QUEKUF that minimizes latency and optimizes resource requirements based upon high-level quantum parameters. Experimental results show that QUEKUF attains up to 7.30× speedup and 81.51× improvement in energy efficiency over a C++ implementation with error-free syndromes while keeping high accuracy.
Quantum Error Correction (QEC) is required in quantum computers to mitigate the effect of errors on physical qubits. When adopting a QEC scheme based on surface codes, error decoding is the most computationally expensive task in the classical electronic back-end. Decoders employing neural networks (NN) are well-suited for this task but their hardware implementation has not been presented yet. This work presents a space exploration of fully-connected feed-forward NN decoders for small distance surface codes. The goal is to optimize the neural network for high decoding performance, while keeping a minimalistic hardware implementation. This is needed to meet the tight delay constraints of real-time surface code decoding. We demonstrate that hardware based NN-decoders can achieve high decoding performance comparable to other state-of-the-art decoding algorithms whilst being well below the tight delay requirements (440 ns) of current solid-state qubit technologies for both ASIC designs (<30 ns) and FPGA implementations (<90 ns). These results indicate that NN-decoders are viable candidates for further exploration of an integrated hardware implementation in future large-scale quantum computers.
The theory of quantum error correction was established decades ago. Yet limitations in physical noise levels and available physical-qubit counts continue to hinder the development of scalable quantum computing systems. In this paper, we present analytical estimates of logical error rates for advanced QEC codes across leading hardware platforms and distributed quantum computing systems using a simple but unified framework. The analysis captures dominant contributors to logical error, including effective circuit volume and two-qubit gate overhead. The framework provides a fast and conservative estimate of logical error rates and identification of dominating factors in different hardware platforms, such as circuit volume, routing overhead, inter-QPU operations, or asymmetric noise protection. We show that several qualitative trends observed in larger-scale simulations can be reproduced and interpreted analytically within this framework. We further demonstrate that the framework can be used to find the sweet spot design region of distributed QEC, which is critical for the design of distributed quantum computing systems.