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EPJ Quantum Technology

Exploring the FPGA and ASIC design space of belief propagation and ordered statistics decoders for quantum error correction codes

Daniel Báscones, Francisco García-Herrero, Javier Valls

Published Nov 20, 2025• 0 citations
Publisher

Abstract

Abstract Belief propagation (BP) combined with ordered statistics decoding (OSD) offers a good balance between accuracy and complexity for many quantum error correction (QEC) codes, making it nearly a universal decoder. However, the complexity of OSD can impose timing constraints on real-time decoding for certain quantum technologies, such as superconducting qubits. Recent experiments have demonstrated that larger time budgets are available for the decoding process. Nevertheless, the limits of classical hardware decoder implementations have not been explored. Therefore, the code distance boundaries for different code families that real-time decoders may support remain unknown. For this reason, it is essential to evaluate the architecture of OSD and explore its limits for code families, such as bicycle bivariate codes and surface codes, under realistic assumptions like the detector error model. The findings from this analysis will benefit not only superconducting qubits but also any quantum technology, as improvements will be advantageous when quantum systems scale up. This paper introduces a BP+OSD parallel architecture implemented in both FPGA and ASIC for various surface codes with distances from 3 to 21 and bicycle bivariate codes ranging from distances 6 to 24. Results indicate that decoders for surface codes can fit into a single VCU129 FPGA up to distance 9, achieving a maximum frequency of 200 MHz and a worst-case latency of 134 \(\mu s\) . For bicycle bivariate codes, the limits are found at distance 12, with a maximum frequency of 244 MHz and a worst-case latency of 84 $\mu s$. In ASIC technology using a 45nm process, the latency limits improve 31%, and area resources explode for the same code distances, making parallel implementation beyond distance 12 impractical in a single chip.The designs proposed in this work have been verified through a hardware emulator to ensure that the behavior of reference codes matches software simulations within a reasonable logical error rate. The behavior of lower regions, previously unexplored with software, has been examined using emulation down to \(10^{-12}\) , generating interesting results, such as changes in the decoder slope that suggest the emergence of an error floor when BP+OSD achieves low logical error rates.

DOI
10.1140/epjqt/s40507-025-00446-y

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Quantum error correction (QEC) is essential for achieving low error rates required for fault-tolerant quantum computation. In stabilizer-based codes such as the surface code, errors are inferred from repeated syndrome measurements and corrected by a classical decoder. To prevent error accumulation, decoding must be performed with both high throughput and low latency to keep pace with the QEC cycle and enable real-time feedback for universal logical operations. Here we report a hardware-integrated control architecture featuring an FPGA-based neural-network (NN) decoder and experimentally demonstrate real-time surface-code (distance-3) QEC on a superconducting quantum processor. The system achieves a deterministic closed-loop latency of 550 ns, including 124 ns for NN decoding, enabling feedback corrections within a 1.25 us QEC cycle. We show that real-time decoding and feedback correction achieve logical performance comparable to offline decoding while maintaining robustness against varying error conditions. We further demonstrate mid-circuit feedback correction in non-Clifford logical circuits, where Pauli-frame updating alone becomes insufficient. Our results establish a low-latency hardware architecture for embedded QEC control and provide a pathway towards scalable fault-tolerant quantum computing systems.
Quantum computers can solve selected problems more efficiently than classical computers, but current devices are limited by high physical error rates. Quantum Error Correction (QEC) mitigates this by encoding many physical qubits into a logical qubit, with the surface code among the most widely studied approaches. Since syndrome measurements are produced continuously, the decoder must process them fast enough to avoid becoming a system bottleneck, making real-time decoding essential for fault-tolerant quantum computing. While most state-of-the-art real-time decoders rely on Minimum-Weight Perfect Matching (MWPM), we instead use a high-accuracy Graph Neural Network (GNN) that trades higher computational cost for lower logical error rates. To make this GNN practical for real-time decoding, we apply algorithm-hardware co-design. We reduce complexity through hardware-guided pruning and retraining, producing two hardware-friendly models that reduce parameter count by 3.1×3.1\times3.1× and 6.5×6.5\times6.5×. These target, respectively, an average decoding latency of one syndrome cycle and a worst-case latency within one syndrome cycle. We further reduce hardware cost using input-graph filtering and post-training quantization. Based on these optimized models, we propose an FPGA-based architecture for low-latency inference and real-time decoding. Evaluated on surface codes up to distance 7 under circuit-level noise at physical error rate p=10−3p=10^{-3}p=10−3, our decoder outperforms MWPM in decoding accuracy for both average-latency and max-latency settings. It reduces logical error rate by 40% at 1μs1μs1μs average latency, and by 13% under a strict 1μs1μs1μs deadline.
Quantum error correction (QEC) is essential for enabling quantum advantages, with decoding as a central algorithmic primitive. Owing to its importance and intrinsic difficulty, substantial effort has been made to QEC decoder design, among which neural decoders have recently emerged as a promising data-driven paradigm. Despite this progress, practical deployment remains hindered by a fundamental accuracy-latency tradeoff, often on the microsecond timescale. To address this challenge, here we revisit neural decoders for surface-code decoding under explicit accuracy-latency constraints, considering code distances up to d=9 (161 physical qubits). We unify and redesign representative neural decoders into five architectural paradigms and develop an end-to-end compression pipeline to evaluate their deployability and performance on FPGA hardware. Through systematic experiments, we reveal several previously underexplored insights: (i) near-term decoding performance is driven more by data scale than architectural complexity; (ii) appropriate inductive bias is essential for achieving high decoding accuracy; and (iii) INT4 quantization is a prerequisite for meeting microsecond-scale latency requirements on FPGAs. Together, these findings provide concrete guidance toward scalable and real-time neural QEC decoding.