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IEEE Computer Society Annual Symposium on VLSI

Bistable All-Josephson Junction SQUID with Dual Φ-Junctions for State-Controlled Superconducting Circuits

Ayisat Adedokun, Yerzhan Mustafa, Selçuk Köse

Published Jul 6, 2025• 1 citation
Publisher

Abstract

A bistable superconducting quantum interference device (SQUID) exclusively comprising Josephson junctions (JJs) is proposed. The design integrates two $2 \Phi$-JJs within the loop structure, while the state of the SQUID is monitored through a conventional $2 \pi$-periodic $\mathbf{J J}$ ($\mathbf{0}$-JJ). This configuration eliminates the need for geometric inductors, leveraging the nonlinear phase dynamics for bistability. Extensive simulations confirm robust bistable operation under controlled external flux bias, positioning the proposed SQUID as an area-efficient building block for superconducting memory cells, sensors for various applications, and SFQ-compatible logic elements.

DOI
10.1109/isvlsi65124.2025.11130322

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A bistable superconducting quantum interference device (SQUID) exclusively comprising Josephson junctions (JJs) is proposed. The design integrates two 2Φ2 \Phi2Φ-JJs within the loop structure, while the state of the SQUID is monitored through a conventional 2π2 \pi2π-periodic JJ\mathbf{J J}JJ (0\mathbf{0}0-JJ). This configuration eliminates the need for geometric inductors, leveraging the nonlinear phase dynamics for bistability. Extensive simulations confirm robust bistable operation under controlled external flux bias, positioning the proposed SQUID as an area-efficient building block for superconducting memory cells, sensors for various applications, and SFQ-compatible logic elements.
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The all-JJ logic family is a promising area and power efficient, scalable single flux quantum (SFQ) technology for application to exascale supercomputers. All-JJ superconductive logic is based on a superconductor-ferromagnet-superconductor (SFS) bistable JJ, enabling nanometer feature sizes in VLSI complexity superconductive systems. In this paper, a mechanical analogy is proposed to describe the dynamic behavior of these bistable JJs. Novel all-JJ logic gates, such as TFF, DFF, OR, AND, and NOT gates, are presented here. All-JJ circuits are composed of bistable JJs, standard JJs, and bias currents, not requiring large inductors within the storage loops. All-JJ logic cells exhibit less delay and power than standard SFQ cells with the same critical current density. All-JJ systems can operate at high frequencies due to the small capacitance of the SFS JJ. A complex all-JJ circuit from the suite of ISCAS'85 benchmark circuits is also characterized. This complex all-JJ circuit exhibits less delay and power as compared to standard SFQ logic. The bias current in a conventional benchmark circuit and all-JJ benchmark circuit is, respectively, 22 mA and 13 mA. The delay of each cell within the conventional benchmark circuit and all-JJ benchmark circuit is, respectively, approximately 20 and 8 ps. A parasitic inductance in series with the JJs disturbs the current distribution within the all-JJ circuits while degrading the margins. To suppress the effects of this parasitic inductance on SFS JJs, small linear inductors are added to manage the current distribution and improve the parameter margins.
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Magnetic flux quantization in superconductors allows the implementation of fast and energy-efficient digital superconducting circuits. However, the information representation in magnetic flux severely limits their functional density presenting a long-standing problem. Here we introduce a concept of superconducting digital circuits that do not utilize magnetic flux and have no inductors. We argue that neither the use of geometric nor kinetic inductance is promising for the deep scaling of superconducting circuits. The key idea of our approach is the utilization of bistable Josephson structures allowing the presentation of information in Josephson energy. Since the proposed circuits functionally rely on Josephson junctions only, they can be called all-Josephson junction (all-JJ) circuits. We consider the design methodology of the all-JJ circuits utilizing recently developed 2ϕ2\phi2ϕ Josephson junctions for simplicity, though the bistability can be obtained with the other types of magnetic junctions like ϕ\phiϕ- or 0−π0-\pi0−π, or by using combinations of conventional 0- and π\piπ-junctions. Besides some broadly used basic cells, we present an all-JJ 8-bit parallel adder confirming the applicability of the proposed approach to the design of complex logic circuits.
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The 2ϕ-Josephson junctions (JJs), characterized by a dominant second harmonic in the current-phase relationship (CPR), are promising devices for low-power, high-density superconducting digital logic. These junctions eliminate the need for on-chip inductors to store magnetic flux and they reduce bias current requirements. In practical implementations, both first and second harmonic components are typically present in the CPR, affecting the junction dynamics and circuit operation. Understanding this behavior is essential for the reliable design of superconducting logic circuits utilizing these junctions, such as half flux quantum (HFQ) circuits. In this article, a compact Verilog-A model for 2ϕ-JJs is presented that captures the nonlinear behavior of the junctions, accounting for both harmonic contributions and their impact on damping. Two parameter sets are derived from experimental data corresponding to junctions with weak ferromagnetic barriers and ferromagnetic insulator barriers. Based on the inferred parameters, models of each junction type are developed. The model is validated against published experimental results and simulated within a D flip flop cell, demonstrating its use for superconducting circuit design and analysis, including evaluation of circuit behavior under nonideal junction conditions. Stability issues and failure mechanisms introduced by a nonzero first harmonic are analyzed, and underlying junction dynamics are examined to explain the reduction in circuit parameter margins.