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International Conference on Transparent Optical Networks

Design of high-voltage electronic driver for polarization encoding quantum transmitters

Hugo Filipe Costa, João G. Prata, Armando N. Pinto, Nelson Jesus Muga

Published Jul 6, 2025• 0 citations
Publisher

Abstract

We present the design and experimental implementation of a compact high-voltage driver tailored for multi-wave-plate electro-optical polarization controllers (EPC) in polarization-based DV-QKD subsystems. The driver is capable of deriving a 140 Vppoutput swing per wave-plate, supports modulation bandwidths up to 7.5MHz, with 10mV resolution, and incorporates per-channel Analog-to-Digital Converter (ADC) monitoring for real-time feedback. A two-stage architecture, with a low-voltage pre-amplification stage followed by a high-voltage output stage, is used with the input being provided by a 16-channel FMC216 Digital-to-Analog Converter (DAC) board, connected to Xilinx Zynq FPGA. Electrical characterization shows that both rise times (∼30ns) and maximum stable square-wave frequency, up to 7.5 MHz, improve as the input Vppincreases, with output gain scaling linearly with input amplitude. Optical testing demonstrates reliable polarization state stability and speed. By enabling fast, precise State of Polarization (SOP) control without bulky stabilization hardware, our driver significantly simplifies the design of polarization-encoded QKD transmitters and receivers, paving the way toward cost-effective, high-rate quantum communications.

DOI
10.1109/icton67126.2025.11125163

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We present the design and experimental implementation of a compact high-voltage driver tailored for multi-wave-plate electro-optical polarization controllers (EPC) in polarization-based DV-QKD subsystems. The driver is capable of deriving a 140 Vppoutput swing per wave-plate, supports modulation bandwidths up to 7.5MHz, with 10mV resolution, and incorporates per-channel Analog-to-Digital Converter (ADC) monitoring for real-time feedback. A two-stage architecture, with a low-voltage pre-amplification stage followed by a high-voltage output stage, is used with the input being provided by a 16-channel FMC216 Digital-to-Analog Converter (DAC) board, connected to Xilinx Zynq FPGA. Electrical characterization shows that both rise times (∼30ns) and maximum stable square-wave frequency, up to 7.5 MHz, improve as the input Vppincreases, with output gain scaling linearly with input amplitude. Optical testing demonstrates reliable polarization state stability and speed. By enabling fast, precise State of Polarization (SOP) control without bulky stabilization hardware, our driver significantly simplifies the design of polarization-encoded QKD transmitters and receivers, paving the way toward cost-effective, high-rate quantum communications.
We present a framework to optimize the voltage range of electro-optic polarization controllers (EPC) in polarization-based quantum key distribution (QKD) subsystems. In this study, we consider an EPC capable of modifying both the phase difference between its fast and slow axes and the orientation of the fast axis. This capability allows it to transform any input state of polarization (SOP) into any desired output SOP on the Poincaré sphere using a single wave-plate. When multiple wave-plates are available, properly distributing the required polarization modulation across them effectively reduces the electronic demands, lowers the implementation costs, and enhances the polarization modulation speeds. This optimization is achieved through the application of multi-objective optimization (MOO) and wave-plate splitting techniques. Within a simulation model, using the calibration parameters from a commercially available six-wave-plate EPC, we determined the optimized voltage ranges required to achieve the six, four, and three SOPs typically used in polarization-based QKD protocols. Two voltage reference points are considered in our study: bias voltage points, which result in zero birefringence, and zero voltage points. For optimization procedures centered around the bias voltage points, we observe a significant reduction in the voltage range, from ±37 V, for a single wave-plate, to approximately ±6 V, for six wave-plates. Furthermore, using wave-plate splitting techniques, we conclude that only two independent wave-plates (four variables) need to be considered in our model to achieve optimized results, which contributes to the efficient design of polarization-based QKD subsystems by minimizing voltage transitions while ensuring precise SOP control, ultimately enabling cost-effective and high-speed polarization modulation.
Quantum Key Distribution (QKD) has garnered significant attention due to its unconditional security based on the fundamental principles of quantum mechanics. While QKD has been demonstrated by various groups and commercial QKD products are available, the development of a fully chip-based QKD system, aimed at reducing costs, size, and power consumption, remains a significant technological challenge. Most researchers focus on the optical aspects, leaving the integration of the electronic components largely unexplored. In this paper, we present the design of a fully integrated electrical control chip for QKD applications. The chip, fabricated using 28 nm CMOS technology, comprises five main modules: an ARM processor for digital signal processing, delay cells for timing synchronization, ADC for sampling analog signals from monitors, OPAMP for signal amplification, and DAC for generating the required voltage for phase or intensity modulators. According to the simulations, the minimum delay is 11ps, the open-loop gain of the operational amplifier is 86.2 dB, the sampling rate of the ADC reaches 50 MHz, and the DAC achieves a high rate of 100 MHz. To the best of our knowledge, this marks the first design and evaluation of a fully integrated driver chip for QKD, holding the potential to significantly enhance QKD system performance. Thus, we believe our work could inspire future investigations toward the development of more efficient and reliable QKD systems.
We present a complete optoelectronic unit for polarization visualization, switching and control. The system is based on an FPGA unit and comprises: an acquisition unit containing an analog polarimeter and digital-to-analog converters, an FPGA capable of implementing an optimal algorithm for three-stage arbitrary polarization tracking, and an electronic driver with analog-to-digital converters capable of interfacing with Lithium-Niobate-based Polarization Controllers. The results, determined via simulation of real-parameter devices, show that fast polarization switch is achievable.
We report the development of an optical assembly and driving electronics for a low-SWaP polarization encoder design for use in satellite-to-ground quantum communication. The optical design multiplexes multiple lasers, which are selectively excited to produce a polarization encoded output. This implementation is intrinsically stable due to the use of only polarization maintaining fiber in the combining optics. The transmitter, provides a low-cost, low-power and high-speed platform to produce polarization encoded pulses. We use the transmitter to generate 4 polarization states with 2 intensity levels via multiplexing of 8 pulsed light sources. The module can generate the polarization states H, V, D and A, which correspond to polarization angles of 0, 90, 45 and -45 degrees respectively, forming two mutually unbiased bases. The transmitter is characterized via a polarization decoder over a free-space link within a laboratory setting. We characterize the source for varying optical channel loss which is introduced between the transmitter and receiver. The transmitter employs the T12 decoy-state BB84 protocol. We explore the performance of the system with commercially available single photon detectors for two clock rates of 500 MHz and 1 GHz. We find a similar secure key rate for both repetition rates, despite the expected 3 dB gain at 1 GHz. This is a result of detector jitter hindering the performance of the QKD system, resulting in a larger QBER when detection events leak into the adjacent time bins and ultimately reduces the secure key rate.
We have developed an electronic hardware system for the control and readout of multi-superconducting qubit devices. The hardware system is based on the design ideas of good scalability, high synchronization and low latency. The system, housed inside a VPX-6U chassis, includes multiple arbitrary-waveform generator (AWG) channels, analog-digital-converter (ADC) channels as well as direct current source channels. The system can be used for the control and readout of up to twelve superconducting transmon qubits in one chassis, and control and readout of more and more qubit can be carried out by interconnecting the chassis. By using field programmable gate array (FPGA) processors, the system incorporates three features that are specifically useful for superconducting qubit research. Firstly, qubit signals can be processed using the on-board FPGA after being acquired by ADCs, significantly reducing data processing time and data amount for storage and transmission. Secondly, different output modes, such as direct output and sequential output modes, of AWG can be implemented with pre-encoded FPGA. Thirdly, with data acquisition ADCs and controlAWGs jointly controlled by the same FPGA, the feedback latency can be reduced, and in ourtest a 178.4 ns latency time is realized. This is very useful for future quantum feedback experiments. Finally, we demonstrate the functionality of the system by applying the system to the control and readout of a 10 qubit superconducting quantum processor.
Quantum key distribution (QKD) research has yielded highly fruitful results and is currently undergoing an industrialization transformation. In QKD systems, electro-optic modulators are typically employed to prepare the required quantum states. While various QKD systems operating at GHz repetition frequency have demonstrated exceptional performance, they predominantly rely on instruments or printed circuit boards to fulfill the driving circuit function of the electro-optic modulator. Consequently, these systems tend to be complex with low integration levels. To address this challenge, we have introduced a modulator driver integrated circuit in 0.18 µm SiGe BiCMOS technology. The circuit can generate multiple-level driving signals with a clock frequency of 1.25 GHz and a rising edge of ∼50 ps. Each voltage amplitude can be independently adjusted, ensuring the precise preparation of quantum states. The measured signal-to-noise ratio was more than 17 dB, resulting in a low quantum bit error rate of 0.24% in our polarization-encoding system. This work will contribute to the advancement of QKD system integration and promote the industrialization process in this field.