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IEEE MTT-S International Microwave Symposium digest

A Cryogenic Front-End Module Applied to Readout Two-Qubits with FDM Technology in Superconducting Quantum Computing System

Che-Hao Li, Chien‐Nan Kuo, Changsheng Chen, Shyh-Shyuan Sheu, Chii-Dong Chen, Po-Yuan Hsu, Li-Chieh Hsiao, Li-Wei Chang

Published Jun 15, 2025• 0 citations
Publisher

Abstract

A massive quantum bits (qubits) array is required to mitigate gate error rates in order to realize a practical quantum computing system. An integrated broadband front-end module is employed for the readout of two transmon qubits using frequency division multiplexing (FDM) technology. The frontend module features a customized IQ up-conversion mixer, fabricated using a$28-\text{nm}$CMOS process, supporting an RF range of$4-10 \text{GHz}$with a conversion gain of$0.3 \pm 3 ~\text{dB}$at 4 K. It achieves sufficient linearity with third-order intermodulation distortion (IM3) exceeding 45 dB and exhibits image rejection ratio (IRR) and LO rejection ratio (LORR) of 57 dB and 50 dB, respectively. The functionality of the front-end module is validated through the successful readout of two qubits. A readout fidelity of around 80 % is measured, consistent with the baseline result.

DOI
10.1109/ims40360.2025.11103873

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A Cryogenic 1.08mW{1.08mW}1.08mW/Qubit Fully-Integrated 4-Channel Frequency-Division-Multiplexing Transmon Qubit State Readout ASIC in 28nm Bulk CMOS
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This work introduces a broadband cryogenic receiver for scalable multiplexed readout of qubits. The receiver utilizes a double quadrature architecture with amplitude and phase error suppression. The hybrid poly-phase filter (PPF) is applied in the architecture to further reduce the input amplitude and phase errors at the radio frequency (RF) end, enhancing the circuit's overall error vector magnitude (EVM). To address the issue of wide bandwidth (BW) for qubit expansion, a low noise amplifier (LNA) with broadband input and noise matching and an improved four-input intermediate frequency amplifier (IF-AMP) with a resistance feedback structure are proposed, achieving a broadband gain response with high flatness. The chip has been designed in standard 55 nm CMOS technology. The LNA achieves a measured power gain of 27.4 dB at 5 GHz with a -3 dB BW of 5.2 GHz at 6 K. Across the entire band of interest, the measured noise figure (NF) deviates by just 0.15 dB from the minimum noise figure (NFmin) and less than 2 dB at 300K, while the measured cryogenic NF falls within the range of 0.79-1 dB. The LNA consumes only 5.5 mW from a 1.2 V supply. Simulation results of the designed receiver indicate that it delivers an average gain of 49.5 dB with a -3 dB BW of 2.4 GHz and an image rejection ratio (IRR) exceeding 40 dB at 300 K.