Abstract Cryogenic control systems are essential for integrating semiconductor spin qubits, and reducing phase noise in phase-locked loop (PLL) frequency synthesizers is critical for high-fidelity spin qubit control. Conventional single-frequency phase noise evaluation methods are not suitable for the multi-frequency demands of spin qubit architectures. To address this, we develop a two-dimensional (2D) phase noise mapping method that evaluates spectral purity as a function of both output and offset frequency. Using a cryogenic fractional-N PLL, we measure phase noise under different reference frequencies and observe frequency dependence of spurious signal. Simulations based on these measurements show infidelity variations up to ∼0.08% across 19.60–20.40 GHz. Our method enables identification of optimal signal configurations and supports resource-efficient design of control electronics. This framework contributes to a practical tool for scaling spin qubit systems and improving signal quality in cryogenic quantum processors.
Abstract Cryogenic control systems are essential for integrating semiconductor spin qubits, and reducing phase noise in phase-locked loop (PLL) frequency synthesizers is critical for high-fidelity spin qubit control. Conventional single-frequency phase noise evaluation methods are not suitable for the multi-frequency demands of spin qubit architectures. To address this, we develop a two-dimensional (2D) phase noise mapping method that evaluates spectral purity as a function of both output and offset frequency. Using a cryogenic fractional-N PLL, we measure phase noise under different reference frequencies and observe frequency dependence of spurious signal. Simulations based on these measurements show infidelity variations up to ∼0.08% across 19.60–20.40 GHz. Our method enables identification of optimal signal configurations and supports resource-efficient design of control electronics. This framework contributes to a practical tool for scaling spin qubit systems and improving signal quality in cryogenic quantum processors.
This article presents a cryo-CMOS quantum controller IC for superconducting qubits. The proposed globally synchronized clock system internally generates different local oscillator (LO) frequencies using multiple phase-locked loops (PLLs) driven by a common reference clock. It provides flexibility in spectral management as well as scalability for expansion to a large-scale quantum controller. The test chip includes two PLLs, four pulse modulator channels, and two receiver channels. Implemented chip in 40-nm CMOS shows full functionalities at 3.5 K. The designed pulse modulator circuits are verified with the specifications for expected fidelity of 99.99%.
Building a large-scale quantum computer requires the co-optimization of both the quantum bits (qubits) and their control electronics. By operating the CMOS control circuits at cryogenic temperatures (cryo-CMOS), and hence in close proximity to the cryogenic solid-state qubits, a compact quantum-computing system can be achieved, thus promising scalability to the large number of qubits required in a practical application. This work presents a cryo-CMOS microwave signal generator for frequency-multiplexed control of 4 × 32 qubits (32 qubits per RF output). A digitally intensive architecture offering full programmability of phase, amplitude, and frequency of the output microwave pulses and a wideband RF front end operating from 2 to 20 GHz allow targeting both spin qubits and transmons. The controller comprises a qubit-phase-tracking direct digital synthesis (DDS) back end for coherent qubit control and a single-sideband (SSB) RF front end optimized for minimum leakage between the qubit channels. Fabricated in Intel 22-nm FinFET technology, it achieves a 48-dB SNR and 45-dB spurious-free dynamic range (SFDR) in a 1-GHz data bandwidth when operating at 3 K, thus enabling high-fidelity qubit control. By exploiting the on-chip 4096-instruction memory, the capability to translate quantum algorithms to microwave signals has been demonstrated by coherently controlling a spin qubit at both 14 and 18 GHz.
Extensive research on quantum mechanics in past decades has successfully paved the way towards the disruptive technology of quantum computing. A further step to the realization of a fault-tolerant scalable quantum computer is presenting challenges in the field of engineering. It necessitates a microsystem operating at 4K in a dilution refrigerator, which would be inevitable to control thousands or millions of qubits sitting at 10mK. There have been IC implementations of pulse modulators generating qubit-controlling microwave signals [1– 4]. The pulse modulation based on direct synthesis demonstrated feasibility of driving multiple qubits with frequency-division multiplexing (FDM) through one RF cable [1 – 3]. The first implementation of a full controller [1], which includes both read and write chains for spin qubits, demonstrated the highest level of integration. However, the previous work used external local oscillator (LO) sources for frequency synthesis. External feeding of LO requires precise matching; otherwise, a failure would cause leakage to the qubit driving output through PCB traces, resulting in AC-Stark shift of qubit state by unwanted tones at near-resonance. It becomes more problematic in FDM-based multi-qubit driving. Since the fidelity of qubit operations strongly relies on the quality of driving frequency, a low-noise LO generation by a phase-locked loop (PLL) is one of the most important factors [5]. The internal generation of LO gives additional benefits in superconducting qubit interface. It necessitates multiple LOs since the superconducting qubit uses microwave pulse driving for both read and write. To detect the state of a qubit through dispersive readout, the phase reflected from the readout resonator should be measured. Therefore, the driving pulses for the read and the write should be synchronized to a single reference timing. Using built-in PLLs sharing a single reference clock naturally solves this problem.
Cryogenic CMOS (cryo-CMOS) quantum bit (qubit) control circuits are expected to overcome the interconnect complexity problem in large-scale quantum computers. However, since each qubit has a unique frequency for control, many power-hungry oscillators are needed to generate the frequencies at the cryogenic temperature stage of a refrigerator. In this paper, to remove the oscillators from the refrigerator, we propose a cryo-CMOS signal selector consisting of two injection-locked oscillators that extract the specified frequency tone for qubit control from the multi-tone microwave signal. This can realize an efficient frequency-multiplexed qubit control system with 1/30 power consumption of the conventional systems.
Cryogenic CMOS (cryo-CMOS) quantum bit (qubit) control circuits are expected to overcome the interconnect complexity problem in large-scale quantum computers. However, since each qubit has a unique frequency for control, many power-hungry oscillators are needed to generate the frequencies at the cryogenic temperature stage of a refrigerator. In this article, to remove the oscillators from the refrigerator, we propose a cryo-CMOS signal selector (SS) consisting of two injection-locked oscillators that extract the specified frequency tone for qubit control from the multitone microwave signal. SS can reduce the power of signal generation for qubit control by 1/30. In addition, we propose a SS with a frequency-doubling function termed FDSS, based on the SS. FDSS can mitigate the local oscillator (LO)-RF leakage in microwave pulse generation for qubit control using direct conversion (DC). We demonstrate a cryo-CMOS DC-based qubit controller using FDSS. The measurement results show that the power dissipation and LO-RF leakage of the proposed qubit controller are reduced by 80% and 20dB, respectively, compared with conventional cryo-CMOS qubit controllers.
Currently, radio frequency (RF) measurement setups for semiconductor qubits are implemented with high performance discrete devices operating at cryogenic temperatures, and the output signals are detected by room temperature instruments.This is impractical for a real quantum processor, and integrated circuits (ICs) should be designed for spin qubit readout in a practical quantum computer, to ensure system reliability and compactness.To guide the system-level IC design, we analyze in this work noise specifications of RF front-end circuits for qubit readout, mainly focusing on noise figure (NF) of the lownoise-amplifier (LNA) and phase noise (PN) of the voltage-controlled-oscillator (VCO).RF reflectometry and RF dispersive gate sensing (DGS) are two main spin qubit readout techniques, both of which should detect weak reflected signals as low as -135 dBm and distinguish <1% amplitude or phase variation, which results in high sensitivity and low noise requirements for the readout circuits, to achieve the high measurement fidelity.For the analysis, we model the RF reflectometry and RF-DGS as demodulators respectively of the on-off keying (OOK) signal and phase modulated (PM) signal from qubits.From this, we provide a first estimation of the required NF and PN for a given fidelity and readout bandwidth, as well as an insight into the relationship between phase resolution of RF-DGS and performance degradation due to PN of the VCO.We then review some state-of-the-art CMOS LNA and VCO topologies, which can be utilized in the spin qubit readout ICs to satisfy the specifications.