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Quantum Information and Computation

Width Optimization of Quantum Circuit Based on Reuse-Aimed Quantum Circuit Transformation

Haotian Tang, Fei Ding, Xueyun Cheng, Shuxian Zhao, Zhijin Guan

Published Jun 1, 2025• 1 citation
Publisher

Abstract

Abstract Due to constraints in current quantum hardware manufacturing, the number of available qubits remains limited. This limitation poses significant challenges to the feasibility of quantum computation. Qubit reuse, supported by the hardware-enabled dynamic quantum circuit, has emerged as a promising method for optimizing the width of quantum circuits. However, enabling width optimization through qubit reuse for circuits that lack qubit reuse opportunities remains a challenging problem. This paper aims to address this challenge by introducing RaQCT (Reuseaimed Quantum Circuit Transformation), an algorithm for converting non-reusable qubit pairs into reusable ones. Moreover, this paper proposes a more general method for identifying reusable qubits based on the perspective of the execution sequence of the quantum gates. Based on the proposed identification method of reusable qubit pairs and RaQCT, this paper proposes width optimization strategies based on a tree structure. Compared with state-of-the-art qubit reuse methods, our proposed methods enable further circuit width optimization, which proves effective. Furthermore, the comprehensive set of methods proposed in this paper for handling qubit reuse does not require specific differentiation of circuit types. Meanwhile, it is applicable to both static and dynamic circuits, thereby also demonstrating generality.

DOI
10.2478/qic-2025-0011

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Abstract Due to constraints in current quantum hardware manufacturing, the number of available qubits remains limited. This limitation poses significant challenges to the feasibility of quantum computation. Qubit reuse, supported by the hardware-enabled dynamic quantum circuit, has emerged as a promising method for optimizing the width of quantum circuits. However, enabling width optimization through qubit reuse for circuits that lack qubit reuse opportunities remains a challenging problem. This paper aims to address this challenge by introducing RaQCT (Reuseaimed Quantum Circuit Transformation), an algorithm for converting non-reusable qubit pairs into reusable ones. Moreover, this paper proposes a more general method for identifying reusable qubits based on the perspective of the execution sequence of the quantum gates. Based on the proposed identification method of reusable qubit pairs and RaQCT, this paper proposes width optimization strategies based on a tree structure. Compared with state-of-the-art qubit reuse methods, our proposed methods enable further circuit width optimization, which proves effective. Furthermore, the comprehensive set of methods proposed in this paper for handling qubit reuse does not require specific differentiation of circuit types. Meanwhile, it is applicable to both static and dynamic circuits, thereby also demonstrating generality.
The practical applications of quantum computing is currently limited by the small number of available qubits. Recent advances in quantum hardware have introduced midcircuit measurements and resets, enabling the reuse of measured qubits and thus reducing the qubit requirements for executing quantum algorithms. In this work, we present a systematic study of dynamic quantum circuit compilation, a process that transforms static quantum circuits into their dynamic equivalents with fewer qubits through qubit reuse. We establish the first graph-based framework for optimizing qubit-reuse compilation. In particular, we characterize the task of finding the optimal compilation strategy for maximizing qubit reuse using binary integer programming and provide efficient heuristic algorithms for devising general compilation strategies. We conduct a thorough analysis of quantum circuits with practical relevance and offer their optimal qubit-reuse compilation strategies. We also perform a comparative analysis against state-of-the-art approaches, demonstrating the superior performance of our methods in both structured and random quantum circuits. Our framework lays a rigorous foundation for understanding dynamic quantum circuit compilation via qubit reuse, holding significant promise for the practical implementation of large-scale quantum algorithms on quantum computers with limited resources.
Qubit reuse offers a promising way to reduce the hardware demands of quantum circuits, but current approaches are largely restricted to reordering measurements and applying qubit resets. In this work, we present an approach to further optimize quantum circuits by fully utilizing the potential of dynamic quantum circuits-more precisely by moving measurements and introducing dynamic circuit primitives such as classically controlled gates in a way that forges entirely new pathways for qubit reuse. This significantly reduces the number of required qubits for a variety of circuits, creating new opportunities for running complex circuits on near-term devices with limited qubit counts. We show that the proposed approach drastically outperforms existing methods, reducing qubit requirements where previous approaches are unable to do so for popular quantum circuits such as Quantum Phase Estimation (QPE), Quantum Fourier Transform~(QFT), and Variational Quantum Eigensolver (VQE) ansätze, as well as leading to improvements of up to 95% for sparse random circuits.
Recent advances in quantum computing introduce the ability to reuse qubits through mid-circuit measurements, thereby enhancing the efficiency of quantum devices with limited computational resources.However, identifying optimal reuse opportunities in quantum circuits remains challenging due to the intricate dependencies between quantum gates.Existing frameworks address this by either directly searching for reuse opportunities or converting circuits into directed acyclic graphs (DAGs).Unfortunately, these frameworks may require exponential search complexity or may not always ensure optimal results due to their non-deterministic property.To overcome these challenges, we propose QR-Map (Qubit Reuse Map), a map-based framework that abstracts computational dependencies for efficient qubit reuse.By extracting and aligning two-qubit gates, QR-Map facilitates dependency detection and ensures qubit savings without incurring excessive idle time.This approach achieves an optimal balance between gate serialization depth and crosstalk reduction.Evaluations with various quantum circuit benchmarks demonstrate that quantum circuits optimized with QR-Map achieve average reductions of 20% in qubit usage, 25% in circuit depth, and 22% in SWAP insertions compared to those optimized with the state-of-the-art framework.
Qubit capacity is a common bottleneck in quantum computers, limiting the ability to run complex algorithms and slowing the advancements in quantum computing applications. Reusing qubits by resetting them after measuring and repurposing them for subsequent gate operations offers an effective strategy to reduce the overall qubit requirements. Based on Satisfiability Modulo Theories (SMT) and Integer Linear Programming (ILP), we present an optimal algorithm that maximizes qubit reuse while optionally constraining the circuit depth to a specified upper bound. Our approach considers all feasible circuit rearrangements to enhance optimality, including gate reordering and eager measurement. We further propose a divide-and-conquer approach to scale for large circuits by relaxing the optimality guarantee. Experimental results show that our exact method substantially decreases both the qubit count and the circuit depth compared to the current state of the art, while the divide-and-conquer approach effectively addresses scalability issues with maintained solution quality.
Quantum computing introduces the challenge of optimizing quantum resources crucial for executing algorithms within the limited qubit availability of current quantum architectures. Existing qubit reuse algorithms face a trade-off between optimality and scalability, with some achieving optimal reuse but limited scalability due to computational complexities, while others exhibit reduced runtime at the expense of optimality. This paper introduces GidNET (Graph-based Identification of qubit NETwork), an algorithm for optimizing qubit reuse in quantum circuits. By analyzing the circuit's Directed Acyclic Graph (DAG) representation and its corresponding candidate matrix, GidNET identifies higher-quality pathways for qubit reuse more efficiently. Through a comparative study with established algorithms, notably QNET [1], GidNET not only achieves a consistent reduction in compiled circuit widths by a geometric mean of 4.4%, reaching up to 21% in larger circuits, but also demonstrates enhanced computational speed and scaling, with average execution time reduction of 97.4% (i.e., 38.5× geometric mean speedup) and up to 99.3% (142.9× speedup) across various circuit sizes. Furthermore, GidNET consistently outperforms Qiskit in circuit width reduction, achieving an average improvement of 59.3%, with maximum reductions of up to 72% in the largest tested circuits. These results demonstrate GidNET's ability to improve circuit width and runtime, offering a solution for quantum computers with limited numbers of qubits.
In recent years, the emergence of the Noisy Intermediate-Scale Quantum (NISQ) era has led to the development of a wide variety of quantum devices, marking a dynamic phase in the field of quantum computing. Despite these advancements, practical applications of quantum computers still face significant challenges, one of the most prominent being the limited connectivity between physical quantum bits (qubits). This limitation requires quantum circuits to be recompiled through layout synthesis before they can be executed on quantum devices. Layout synthesis determines the specific placement of quantum gates within the circuit on the physical hardware. When gates do not align with the connectivity constraints of the device, additional quantum gates must be inserted to remap the qubits, which can negatively affect the circuit’s efficiency and performance. To address this issue, the primary goal of this paper is to enhance the mapping process within layout synthesis, aiming to optimize both the layout and the circuit depth. Experimental results demonstrate that the proposed method effectively reduces the quantum circuit depth, outperforming other existing approaches in terms of efficiency.