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arXiv:2410.08817 · IEEE International Conference on Quantum Computing and Engineering (QCE)

Graph-Based Identification of Qubit Network (GidNET) for Qubit Reuse

Gideon Uchehara, Tor M. Aamodt, Olivia Di Matteo

Published Sep 15, 2024• 4 citations
arXivHTMLPDF

Abstract

Quantum computing introduces the challenge of optimizing quantum resources crucial for executing algorithms within the limited qubit availability of current quantum architectures. Existing qubit reuse algorithms face a trade-off between optimality and scalability, with some achieving optimal reuse but limited scalability due to computational complexities, while others exhibit reduced runtime at the expense of optimality. This paper introduces GidNET (Graph-based Identification of qubit NETwork), an algorithm for optimizing qubit reuse in quantum circuits. By analyzing the circuit's Directed Acyclic Graph (DAG) representation and its corresponding candidate matrix, GidNET identifies higher-quality pathways for qubit reuse more efficiently. Through a comparative study with established algorithms, notably QNET [1], GidNET not only achieves a consistent reduction in compiled circuit widths by a geometric mean of 4.4%, reaching up to 21% in larger circuits, but also demonstrates enhanced computational speed and scaling, with average execution time reduction of 97.4% (i.e., 38.5× geometric mean speedup) and up to 99.3% (142.9× speedup) across various circuit sizes. Furthermore, GidNET consistently outperforms Qiskit in circuit width reduction, achieving an average improvement of 59.3%, with maximum reductions of up to 72% in the largest tested circuits. These results demonstrate GidNET's ability to improve circuit width and runtime, offering a solution for quantum computers with limited numbers of qubits.

DOI
10.1109/qce60285.2024.00131

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Abstract Due to constraints in current quantum hardware manufacturing, the number of available qubits remains limited. This limitation poses significant challenges to the feasibility of quantum computation. Qubit reuse, supported by the hardware-enabled dynamic quantum circuit, has emerged as a promising method for optimizing the width of quantum circuits. However, enabling width optimization through qubit reuse for circuits that lack qubit reuse opportunities remains a challenging problem. This paper aims to address this challenge by introducing RaQCT (Reuseaimed Quantum Circuit Transformation), an algorithm for converting non-reusable qubit pairs into reusable ones. Moreover, this paper proposes a more general method for identifying reusable qubits based on the perspective of the execution sequence of the quantum gates. Based on the proposed identification method of reusable qubit pairs and RaQCT, this paper proposes width optimization strategies based on a tree structure. Compared with state-of-the-art qubit reuse methods, our proposed methods enable further circuit width optimization, which proves effective. Furthermore, the comprehensive set of methods proposed in this paper for handling qubit reuse does not require specific differentiation of circuit types. Meanwhile, it is applicable to both static and dynamic circuits, thereby also demonstrating generality.
Recent advances in quantum computing introduce the ability to reuse qubits through mid-circuit measurements, thereby enhancing the efficiency of quantum devices with limited computational resources.However, identifying optimal reuse opportunities in quantum circuits remains challenging due to the intricate dependencies between quantum gates.Existing frameworks address this by either directly searching for reuse opportunities or converting circuits into directed acyclic graphs (DAGs).Unfortunately, these frameworks may require exponential search complexity or may not always ensure optimal results due to their non-deterministic property.To overcome these challenges, we propose QR-Map (Qubit Reuse Map), a map-based framework that abstracts computational dependencies for efficient qubit reuse.By extracting and aligning two-qubit gates, QR-Map facilitates dependency detection and ensures qubit savings without incurring excessive idle time.This approach achieves an optimal balance between gate serialization depth and crosstalk reduction.Evaluations with various quantum circuit benchmarks demonstrate that quantum circuits optimized with QR-Map achieve average reductions of 20% in qubit usage, 25% in circuit depth, and 22% in SWAP insertions compared to those optimized with the state-of-the-art framework.
The practical applications of quantum computing is currently limited by the small number of available qubits. Recent advances in quantum hardware have introduced midcircuit measurements and resets, enabling the reuse of measured qubits and thus reducing the qubit requirements for executing quantum algorithms. In this work, we present a systematic study of dynamic quantum circuit compilation, a process that transforms static quantum circuits into their dynamic equivalents with fewer qubits through qubit reuse. We establish the first graph-based framework for optimizing qubit-reuse compilation. In particular, we characterize the task of finding the optimal compilation strategy for maximizing qubit reuse using binary integer programming and provide efficient heuristic algorithms for devising general compilation strategies. We conduct a thorough analysis of quantum circuits with practical relevance and offer their optimal qubit-reuse compilation strategies. We also perform a comparative analysis against state-of-the-art approaches, demonstrating the superior performance of our methods in both structured and random quantum circuits. Our framework lays a rigorous foundation for understanding dynamic quantum circuit compilation via qubit reuse, holding significant promise for the practical implementation of large-scale quantum algorithms on quantum computers with limited resources.
The growing variety of quantum hardware technologies, each with unique peculiarities such as connectivity and native gate sets, creates challenges when selecting the best platform for executing a specific quantum circuit. This selection process usually involves a brute-force approach: compiling the circuit on various devices and evaluating performance based on factors such as circuit depth and gate fidelity. However, this method is computationally expensive and does not scale well as the number of available quantum processors increases. In this work, we propose a Graph Neural Network (GNN)based predictor that automates hardware selection by analyzing the Directed Acyclic Graph (DAG) representation of a quantum circuit. Our study evaluates 498 quantum circuits (up to 27 qubits) from the MQT Bench dataset, compiled using Qiskit on four devices: three superconducting quantum processors (IBM-Kyiv, IBM-Brisbane, IBM-Sherbrooke) and one trappedion processor (IONQ-Forte). Performance is estimated using a metric that integrates circuit depth and gate fidelity, resulting in a dataset where 93 circuits are optimally compiled on the trappedion device, while the remaining circuits prefer superconducting platforms. By exploiting graph-based machine learning, our approach avoids extracting the circuit features for the model evaluation but directly embeds it as a graph, significantly accelerating the optimal target decision-making process and maintaining all the information. Experimental results prove94.4%\mathbf{9 4. 4 \%}94.4%accuracy and an85.5%\mathbf{8 5. 5 \%}85.5%F1 score for the minority class, effectively predicting the best compilation target. The developed code is publicly available on GitHub (https://github.com/antotu/GNN-Model-Quantum-Predictor).
Quantum circuit optimization is a key step toward the efficient execution of quantum algorithms. Template matching has emerged as one of the dominant approaches for simplifying quantum circuits, yet it confronts the intrinsic challenge of accommodating gate commutativity. The state-of-the-art template-matching algorithm relies on a directed acyclic graph (DAG) representation. While this DAG-based technique handles gate commutativity satisfactorily, it fails to preserve the local connectivity inherent to quantum circuits, thereby leading to relatively high matching complexity. In this paper, we introduce a hypergraph representation (HG), a commutativity-aware representation that collapses commuting gates into a single super-node while retaining all local connectivity. This enables matches to be extended locally without revisiting the rest of the circuit, with incremental updates limited to the immediate neighborhood. Experimental results demonstrate that our HG matcher achieves 11--606x speed-up over the DAG-based implementation in Qiskit (Iten et al., 2022) on both random and arithmetic benchmarks, while maintaining the same optimization quality. The acceleration increases with circuit size, confirming that preserving locality and connectivity is the key to scalable quantum circuit optimisation.
Quantum computing is widely regarded as a promising technology due to its potential to offer exponential computational advantages over classical systems. However, practical deployment and realization of most quantum algorithms remain constrained by the limitations of current quantum architectures– most notably, the limited number of physical qubits available in quantum processing units (QPUs). Therefore, efficient utilization of quantum resources has become a crucial concern in the field. Thus, in this paper, we explore the nature of qubit reuse. Based on our findings, we formulate an optimization problem and propose a novel algorithm to minimize the number of qubits for scheduled quantum circuits. Finally, extensive simulation results on various practical benchmarks manifest that our algorithm can significantly outperform the existing approach in qubit reuse.