Abstract Scalable solutions are essential to achieving the long-term goal of building a fault-tolerant quantum computer and energy-power consumption are fundamental limiting factors for this target. Among the available types of silicon qubits, this work focuses on Flip-Flop (FF) qubits. Energy consumption and power requirements are estimated for a square array of qubits that hosts the logical qubit. The logical qubit is implemented using the rotated Surface Code (SC) for Quantum Error Correction (QEC). By using a universal set of quantum gates, the energy usage, time and power requirements for a SC cycle are estimated based on noise level, code distance and control levels. These estimates are used to provide insights into the main scaling-up challenges for quantum computer development. This is achieved by extending a thermal model that includes energy contributions from both the cryogenic components (such as the qubit array, the cryogenic control electronics, and the cryostat) and the room temperature (RT) section (RT electronics and heat dissipation systems). The maximum numbers of physical and logical qubits are provided, as well as power consumption across the different temperature sections.
Abstract Scalable solutions are essential to achieving the long-term goal of building a fault-tolerant quantum computer and energy-power consumption are fundamental limiting factors for this target. Among the available types of silicon qubits, this work focuses on Flip-Flop (FF) qubits. Energy consumption and power requirements are estimated for a square array of qubits that hosts the logical qubit. The logical qubit is implemented using the rotated Surface Code (SC) for Quantum Error Correction (QEC). By using a universal set of quantum gates, the energy usage, time and power requirements for a SC cycle are estimated based on noise level, code distance and control levels. These estimates are used to provide insights into the main scaling-up challenges for quantum computer development. This is achieved by extending a thermal model that includes energy contributions from both the cryogenic components (such as the qubit array, the cryogenic control electronics, and the cryostat) and the room temperature (RT) section (RT electronics and heat dissipation systems). The maximum numbers of physical and logical qubits are provided, as well as power consumption across the different temperature sections.
Semiconductor spin qubits offer a promising route to compact and scalable quantum computers, combining long coherence times in isotopically purified silicon with compatibility with semiconductor manufacturing. Beyond computational speedup, their energy efficiency is an important consideration for future large-scale systems. We evaluate the power and energy requirements of a Loss-DiVincenzo spin-qubit quantum computer by analyzing the Quantum Fourier Transform (QFT) and benchmarking it against the classical Fast Fourier Transform (FFT). We develop a detailed energy budget, identifying cryogenic cooling as the dominant baseline contribution before quantum error correction (QEC). The comparison between the QFT and the classical FFT reveals that, for any quantum workload operating under a polynomially bounded sampling regime, the crossover in energy consumption occurs at smaller problem sizes than the crossover in execution time. Thus, quantum computing can become energetically competitive before achieving a speedup in execution time. We then incorporate surface-code QEC and analyze the energy costs of QEC cycles, gate synthesis, and decoding. At scale, instrumentation and decoding become dominant contributions, while cryogenic cooling imposes a constraint on scalability. We show that optimizing the control-signal demultiplexing ratio can reduce the overall energy cost by approximately two orders of magnitude. For a system with about one million physical qubits, we estimate a power consumption of approximately 100 kW, at least one order of magnitude below that of today's highest-performance classical computing systems.
Surface codes are crucial for fault-tolerant quantum computing (FTQC) and rely on syndrome analysis to identify quantum errors. Superconducting qubits are operating at extremely low temperatures, but the room-temperature syndrome analyzer limits scalability. This paper explores syndrome analysis at an intermediate temperature (around 4 K) and focuses on a hardware-friendly exhaustive search algorithm. Results show that using 4-bit weights enables error correction with a code distance of 5 and a physical error rate of 10−4. The energy consumption per logical qubit per error correction is1.13×10−3nJ, supporting up to 8.86×105logical qubits in a cryogenic environment.
Silicon spin qubits are a leading candidate for large-scale quantum computing owing to their compatibility with semiconductor manufacturing. However, scaling to useful fault-tolerant processors will likely generate thermal loads that exceed the cooling power available at millikelvin temperatures. Raising the operating temperature eases cooling requirements but reduces gate fidelity, increasing the overhead of quantum error correction. Identifying the operating temperature that minimizes total power consumption is therefore a key challenge for commercially viable quantum computers. Here, we use gate set tomography to benchmark two-qubit silicon chips fabricated in both industrial and academic environments over a range of temperatures. Elevated temperatures substantially shorten coherence times and increase gate and state-preparation-and-measurement infidelities. Based on these measurements, we develop a general power model for silicon quantum computers that combines cryogenic cooling requirements with error-correction overheads. We show that a finite optimal operating temperature exists and is strongly influenced by a crossover temperature near 1 K in current devices, above which gate fidelity degrades rapidly. These results connect device-level fidelity limitations to system-level power requirements, providing design guidelines for large-scale silicon quantum computers.
Surface-code quantum error correction (QEC) is pivotal for fault-tolerant quantum computing, but its energy efficiency remains underexplored. This work derives a practical lower bound on the energy cost per logical-qubit operation, accounting for gate-fidelity decay's impact on code distance and physical-qubit overhead. By modeling the energy consumption of gate operations and error correction, we express the total cost as $ E = (E_g N_g + E_c N_c)/N_l $, where $ E_g $, $ E_c $, $ N_g $, $ N_c $, and $ N_l $ represent gate and physical-qubit energy costs, gate counts, physical-qubit counts, and logical qubit counts, respectively. Gate-fidelity decay increases the required code distance $ d $, scaling $ N_c $ and thus $ E $. We propose normalizing computational cost in joules per logical-qubit operation (JPCUB), isolating logical work from error-correction overhead. Quantitative predictions for $ E_g $, $ E_c $, and $ N_c $ remain [to verify], but the functional dependence on $ d $ and gate fidelities is established. This framework informs energy-efficient QEC design and benchmarks. ## 1. Introduction Surface codes enable fault-tolerant quantum computation by encoding logical qubits in a 2D lattice of physical qubits, correcting errors through syndrome measurements. However, the energy cost per logical operation—critical for scalability—remains poorly quantified. While theoretical foundations exist (Raussendorf & Terhal, 2006; Kitaev, 2003), prior work focuses on error-correction thresholds rather than energy efficiency. Here, we address this gap by deriving a lower bound on energy cost, considering how gate-fidelity decay necessitates larger code distances $ d $, increasing physical-qubit overhead $ N_c $. This analysis connects to the joules-per-compute (JPCUB) benchmark, advocating for energy normalization per logical qubit to disentangle computational work from error-correction costs. ## 2. Background Surface codes encode logical qubits using a 2D grid of
Scaling fault tolerant quantum computers, especially cryogenic systems based on the surface code, to millions of qubits is challenging due to poorly-scaling data processing and power consumption overheads. One key hurdle is the design of real-time quantum error correction (QEC) decoders, which demands high data rates for error processing; this is particularly apparent in systems with cryogenic qubits and room temperature (RT) decoders. In response, cryogenic predecoding using lightweight logic has been proposed to handle sparse errors in the cryogenic domain. However, prior work only accounts for a subset of error sources in real-world quantum systems with limited accuracy, often degrading performance below useful levels in practical scenarios. Moreover, prior reliance on SFQ logic precludes detailed architecture-technology co-optimization.
To address these limitations, this paper introduces Pinball, a comprehensive design in cryogenic CMOS of a QEC predecoder for the surface code tailored to realistic, circuit-level noise. By accounting for error generation and propagation through QEC circuits, our design achieves higher predecoding accuracy, outperforming logical error rates (LER) of the current state-of-the-art (SOTA) cryogenic predecoder by nearly six orders of magnitude. Remarkably, despite operating under much stricter power and area constraints, Pinball also reduces LER by 32.58x and 5x, respectively, compared to SOTA RT predecoder and RT ensemble configurations. By increasing cryogenic coverage, we also reduce syndrome bandwidth up to 3780.72x. Through co-design with 4 K-characterized 22nm FDSOI technology, we achieve peak power consumption under 0.56 mW. Voltage/frequency scaling and body biasing enable 22.2x lower typical power consumption, yielding up to 67.4x total energy savings. Assuming a 1.5 W 4 K power budget, our predecoder supports up to 2,668 logical qubits at d=21.
A fault tolerant scalable quantum computer requires more than 1000 Qubits to perform real time state correction and to improve the Qubit coherence time. The dense wiring connections required between the quantum processor placed at a 100 mK temperature and the room temperature control and readout electronics serve as a limiting factor in this system. Qubit control and readout electronics operating at 4 K temperature, placed closer to a quantum processor inside the dilution refrigerator avoids the dense wiring connections to room temperature electronics, and hence, serve as a potential solution to realize a scalable quantum computer. However, with no CMOS process technology models available at cryogenic temperatures, the design of a fully integrated, ultra-low power Qubit control and readout electronics at a sub-1 mW power consumption proves to be extremely challenging. In recent years, there has been a huge rise in interest among the research communities to understand and solve the device and circuit level challenges at deep cryogenic temperatures. This paper presents an overview of the recently published active and passive device nonidealities, circuit design challenges and solutions, and the future research directions in the Qubit control and readout electronics operating at deep cryogenic temperatures.