Measurement setup for the characterization of integrated semiconductor circuits at cryogenic temperatures
Paul Julius Ritter, Marc-André Tucholke, Marius Neumann, Julius Mumme, Alexander Meyer, R. Roederer, Z. Guo, Andreas Pawlak, Вадим Іссаков, Meinhard Schilling, Benedikt Hampel
Integrated semiconductor circuits operating at cryogenic temperatures can play a crucial role in scaling quantum computing architectures based on trapped-ion and superconducting qubits. Other technologies, such as low-temperature detectors, can also benefit significantly from these circuits. These applications demand high-frequency, cryogenic temperature measurement systems for the thorough characterization of semiconductor components and circuits. This work presents a customizable, high-frequency, fast, and reliable cryogenic measurement setup for measurement temperatures ranging from room temperature to 4.2 K. It features up to two dc probes or two ground-signal-ground probes for frequencies of up to 67 GHz, which can be configured in a 180° or 90° configuration. In addition, up to 48 BeCu wires configured as twisted pairs provide supply and control signals. Furthermore, up to four rf connections can be mounted directly to a printed circuit board. The setup features an optical microscope in the vacuum chamber to position the probes, which is further utilized by a machine vision algorithm, allowing the detection of pads and automatic positioning of the probes over the pads. The hardware is located in a 550 × 500 × 500 mm3 large vacuum chamber with two independent pulse tube cryocoolers with cooling powers of up to 0.9 and 0.4 W at 4.2 K. Exemplary room temperature and cryogenic S-parameter, transient frequency (fT), time-domain, capacitance-voltage, and dc measurements of single transistors and integrated circuits fabricated by Infineon are presented, demonstrating the system's measurement capability for quantum computing and other applications.
Integrated semiconductor circuits operating at cryogenic temperatures can play a crucial role in scaling quantum computing architectures based on trapped-ion and superconducting qubits. Other technologies, such as low-temperature detectors, can also benefit significantly from these circuits. These applications demand high-frequency, cryogenic temperature measurement systems for the thorough characterization of semiconductor components and circuits. This work presents a customizable, high-frequency, fast, and reliable cryogenic measurement setup for measurement temperatures ranging from room temperature to 4.2 K. It features up to two dc probes or two ground-signal-ground probes for frequencies of up to 67 GHz, which can be configured in a 180° or 90° configuration. In addition, up to 48 BeCu wires configured as twisted pairs provide supply and control signals. Furthermore, up to four rf connections can be mounted directly to a printed circuit board. The setup features an optical microscope in the vacuum chamber to position the probes, which is further utilized by a machine vision algorithm, allowing the detection of pads and automatic positioning of the probes over the pads. The hardware is located in a 550 × 500 × 500 mm3 large vacuum chamber with two independent pulse tube cryocoolers with cooling powers of up to 0.9 and 0.4 W at 4.2 K. Exemplary room temperature and cryogenic S-parameter, transient frequency (fT), time-domain, capacitance-voltage, and dc measurements of single transistors and integrated circuits fabricated by Infineon are presented, demonstrating the system's measurement capability for quantum computing and other applications.
Thousands to millions of sensitive signals will need to be conveyed through all the temperature stages of a dilution fridge to operate future large-scale quantum processors made of many quantum bits. The exploding number of heat-conductive coaxial cables will overwhelm the fridge cooling capabilities, detrimental to the quantum core. Moving the control electronics down to cryogenic temperatures allows the use of already-available superconducting cables, alleviating heat conduction between low-temperature stages, and appears as a clear path towards scalability in the number of operating qubits.This Ph.D. work aimed to explore the use of the industrial CMOS 28nm Fully-Depleted Silicon-On-Insulator (FD-SOI) technology at cryogenic temperatures for quantum computing applications. Our first objective is to extend the sparse existing knowledge about the FD-SOI 28nm transistors at cryogenic temperatures for practical aspects of circuit design and later for developments of compact models.To speed-up the characterization of single devices with the inherent hour-long cooling cycles, we designed an integrated circuit multiplexing a thousand of transistors for different geometries and gate-stack flavors for low-frequency measurement of the current-voltage characteristics and pair-matching analysis from 300 down to 0.1K. We discuss and analyze the evolution trends with varying geometry at different temperatures for important quantities in circuit design, such as the transconductance, the conductance, and the transconductance over drain current ratio of individual transistors.Secondly, we explore the low-temperature co-integration and the full on-chip integration of semiconductor quantum devices with classical electronics aimed at specific measurements down to the millikelvin range.We first focus on the sub-nanoampere current measurement of quantum dot devices by designing and characterizing a low-power transimpedance amplifier (TIA). The high-gain amplifier is successfully applied to measure the current across single- and double quantum-dot devices, respectively wire-bonded a few mm away or on-chip integrated a few micrometers-away. To further leverage the integration into the same substrate, we connected GHz-range voltage-controlled oscillators to one of the gates of the double dot in an attempt to observe discrete charge pumping in a fully-integrated device.Lastly, we tackled the measurement of the gate capacitance of single quantum devices by proposing a new measurement scheme making use of the cryogenic electronics capabilities as an alternative to the well-known reflectometry. By integrating a voltage-controlled current excitation and a voltage-sensing amplifier in the 200 MHz range, both in close proximity to the quantum device connected to an LC tank, the read-out circuitry of a variation in the device capacitance becomes a purely lumped-element system with impedance measurement of the resonant circuit without any wave propagation like in reflectometry. This approach increases simplicity and compactness of the measurement set-up. We even replace the bulky passive inductor used in reflectometry by an active inductor made of transistors and capacitors, offering improved scalability with a 3-orders of magnitude lower area for the same inductance. The resulting circuit successfully measured aF-capacitance variations of nanometric transistors at 4.2K revealing oscillatory quantum effects in the gate capacitance as a function of the gate and back-gate voltages.At the end of this dissertation, a picture is given with the challenges laying ahead related to circuit architecture and design for the ultimate goal of entering into the era of large-scale quantum processing.
Quantum computing promises an exponential speed-up of computation compared to what is nowadays achievable with classical computers. In this way, it enables the evaluation of more complex models and the breaching of current security algorithms. For the operation of a quantum system, many questions remain to be answered. Currently, there are several quantum technologies that promise to be both reliable and scalable, two features required for large scale quantum operations. Common to all technologies is the operating temperature that needs to be close to absolute zero, i.e. below 100 mK, to suppress environment noise and allow the quantum properties to become 'visible'. In order for any quantum processor to be operated, a so-called quantum-classical interface is required for the quantum bit (qubit) read-out and control. This interface consists of various electronic blocks, such as analog-to-digital converters, digital-to-analog converters, mixers, amplifiers and a digital controller. Especially the analog blocks require effort to meet the noise and stability constraints as not to disturb the very sensitive qubits and allow reading of the tiny signals. As the qubits live in extremely deep-cryogenic temperatures, long wires interface the cryogenic with the room temperature environment, where most of the electronics is situated. However, for a scalable system, heat injection becomes a serious problem, with many wires between 300 K and sub-Kelvin. Furthermore, such amount of interconnects is challenging to mechanically place in a dilution refrigerator. Therefore, in this work, we propose to implement the electronics not at room temperature, but at a temperature much closer to the qubits, for example at 4 K. This not only reduces significantly the wiring between room temperature and the qubits, but we can also benefit from lower electronic noise at such a temperature. The operation of conventional electronics almost 200°C below its normal temperature range is not trivial as device properties alter significantly and most circuits no longer operate as intended. In CMOS processes, the main technology in the integrated electronics world, the behaviour of the transistors, required for the implementation of any circuit, deviates considerably at low temperatures. The transistor's threshold voltage goes up, the mobility increases and the subthreshold slope becomes steeper, to name just a few of these deviations. Although there are improvements in performance, there are also some counter effects, and characterization of the transistors is needed to observe the changes. Once devices are characterized at such low temperatures, new models can be built and circuits can be simulated and adapted to operate properly at cryogenic temperatures. Luckily, there are various commercially available devices that can already withstand the chills of cold. We demonstrated various commercially available devices, such as a field-programmable gate array (FPGA) implemented in a 28 nm CMOS process, to be operating without major concerns at 4~K. Its properties alter only slightly, within 5 to 10%, and all tested circuit implementations, working at 300~K, also worked at 4 K. We combined both commercially available devices, that operate 200 K below their specified temperature range, with custom designed CMOS circuits to implement a cryogenic read-out platform for spin qubits. This system comprises amplifiers, an ADC, an FPGA, voltage regulators and a clock generator. It allows to amplify the tiny signal from the qubits and digitize it directly in the FPGA in order to process the data locally at 4~K. This system is one of the first systematic attempts at operating a part of the quantum-classical interface at cryogenic temperatures and forms the basis for future systems comprising the complete electronic interface for qubits to operate at such low temperatures. One of the main problems to tackle for cryogenic electronic systems is their power consumption. Power budgets are simply limited to roughly 1 or 2 Watts at 4 K and exponentially lower at deeper cryogenic temperatures, thus limiting the size of large-scale electronic systems. Our approach of combined commercial and custom circuits will have to be steadily replaced by a single (custom) technology that meets both power and scalability constraints. One of the best candidates is CMOS, a technology that the industry has relied upon for several decades and benefits from many optimizations thanks to Moore's law.
This thesis proposes a pathway to realizing large-scale quantum computing integrated circuits based on the monolithic integration of high-temperature (1–4 K) semiconductor qubits with their associated control and readout circuitry. High-frequency device characterization was performed on production 22-nm FDSOI technology at room and cryogenic temperatures (down to 3.3 K) to inform a cryogenic circuit design methodology in the absence of low-temperature device models. The methodology was demonstrated with a TIA qubit-readout chain that was, for the first time, monolithically integrated with electron and hole quantum dot structures. The prospects of FDSOI SiGe BiCMOS technology would enable similar integration with higher performance HBT devices. As a first step, design of a 240-GHz direct conversion I-Q receiver is showcased in 55-nm SiGe BiCMOS, intended for frequency-division multiplexed readout of many qubits. The measured IF-bandwidth of 59 GHz makes it suitable for high data-rate communication and large-scale quantum processors.
Fast feedback from cryogenic electrical characterization measurements is key for the development of scalable quantum computing technology. At room temperature, high-throughput device testing is accomplished with a probe-based solution, where electrical probes are repeatedly positioned onto devices for acquiring statistical data. In this work, we present a probe station that can be operated from room temperature down to below 2 K. Its small size makes it compatible with standard cryogenic measurement setups with a magnet. A large variety of electronic devices can be tested. Here, we demonstrate the performance of the prober by characterizing silicon fin field-effect transistors as a host for quantum dot spin qubits. Such a tool can massively accelerate the design-fabrication-measurement cycle and provide important feedback for process optimization toward building scalable quantum circuits.
We have developed a cryogenic probe and cryostat system to test both active and passive superconducting devices and circuits up to microwave frequencies at variable temperatures. Our system consists of two basic parts: the cryostat and the matching probe. The cryostat is a unique, very efficient, variable temperature, flow-type cryostat, where we control temperature without electrical heaters. It is magnetically shielded and allows rapid testing between 4.2 K and room temperature. Probes developed for this cryostat have a larger number of shorter cables than standard dip-type probes. They are designed to test chips or chip assemblies without additional packaging. Chips or chip assemblies can be quickly mounted and dismounted from a fixed spring-contact assembly. Each probe has 56 wide-bandwidth signal cables. We have repeatedly used these probes for testing both active and passive superconducting integrated circuits up to 20 GHz. The probe and cryostat combination provides a testing capability that is simultaneously high frequency, dc magnetic shielded, has variable cryogenic temperature, and quick turnaround.
We have developed a cryogenic platform for the control and readout of spin qubits that comprises a high density of dc and radio frequency sample interconnects based on a set of coupled printed circuit boards. The modular setup incorporates 24 filtered dc lines, 14 control and readout lines with bandwidth from dc to above 6 GHz, and 2 microwave connections for excitation to 40 GHz. We report the performance of this platform, including signal integrity and crosstalk measurements and discuss design criteria for constructing sample interconnect technology needed for multi-qubit devices.