Thousands to millions of sensitive signals will need to be conveyed through all the temperature stages of a dilution fridge to operate future large-scale quantum processors made of many quantum bits. The exploding number of heat-conductive coaxial cables will overwhelm the fridge cooling capabilities, detrimental to the quantum core. Moving the control electronics down to cryogenic temperatures allows the use of already-available superconducting cables, alleviating heat conduction between low-temperature stages, and appears as a clear path towards scalability in the number of operating qubits.This Ph.D. work aimed to explore the use of the industrial CMOS 28nm Fully-Depleted Silicon-On-Insulator (FD-SOI) technology at cryogenic temperatures for quantum computing applications. Our first objective is to extend the sparse existing knowledge about the FD-SOI 28nm transistors at cryogenic temperatures for practical aspects of circuit design and later for developments of compact models.To speed-up the characterization of single devices with the inherent hour-long cooling cycles, we designed an integrated circuit multiplexing a thousand of transistors for different geometries and gate-stack flavors for low-frequency measurement of the current-voltage characteristics and pair-matching analysis from 300 down to 0.1K. We discuss and analyze the evolution trends with varying geometry at different temperatures for important quantities in circuit design, such as the transconductance, the conductance, and the transconductance over drain current ratio of individual transistors.Secondly, we explore the low-temperature co-integration and the full on-chip integration of semiconductor quantum devices with classical electronics aimed at specific measurements down to the millikelvin range.We first focus on the sub-nanoampere current measurement of quantum dot devices by designing and characterizing a low-power transimpedance amplifier (TIA). The high-gain amplifier is successfully applied to measure the current across single- and double quantum-dot devices, respectively wire-bonded a few mm away or on-chip integrated a few micrometers-away. To further leverage the integration into the same substrate, we connected GHz-range voltage-controlled oscillators to one of the gates of the double dot in an attempt to observe discrete charge pumping in a fully-integrated device.Lastly, we tackled the measurement of the gate capacitance of single quantum devices by proposing a new measurement scheme making use of the cryogenic electronics capabilities as an alternative to the well-known reflectometry. By integrating a voltage-controlled current excitation and a voltage-sensing amplifier in the 200 MHz range, both in close proximity to the quantum device connected to an LC tank, the read-out circuitry of a variation in the device capacitance becomes a purely lumped-element system with impedance measurement of the resonant circuit without any wave propagation like in reflectometry. This approach increases simplicity and compactness of the measurement set-up. We even replace the bulky passive inductor used in reflectometry by an active inductor made of transistors and capacitors, offering improved scalability with a 3-orders of magnitude lower area for the same inductance. The resulting circuit successfully measured aF-capacitance variations of nanometric transistors at 4.2K revealing oscillatory quantum effects in the gate capacitance as a function of the gate and back-gate voltages.At the end of this dissertation, a picture is given with the challenges laying ahead related to circuit architecture and design for the ultimate goal of entering into the era of large-scale quantum processing.
Thousands to millions of sensitive signals will need to be conveyed through all the temperature stages of a dilution fridge to operate future large-scale quantum processors made of many quantum bits. The exploding number of heat-conductive coaxial cables will overwhelm the fridge cooling capabilities, detrimental to the quantum core. Moving the control electronics down to cryogenic temperatures allows the use of already-available superconducting cables, alleviating heat conduction between low-temperature stages, and appears as a clear path towards scalability in the number of operating qubits.This Ph.D. work aimed to explore the use of the industrial CMOS 28nm Fully-Depleted Silicon-On-Insulator (FD-SOI) technology at cryogenic temperatures for quantum computing applications. Our first objective is to extend the sparse existing knowledge about the FD-SOI 28nm transistors at cryogenic temperatures for practical aspects of circuit design and later for developments of compact models.To speed-up the characterization of single devices with the inherent hour-long cooling cycles, we designed an integrated circuit multiplexing a thousand of transistors for different geometries and gate-stack flavors for low-frequency measurement of the current-voltage characteristics and pair-matching analysis from 300 down to 0.1K. We discuss and analyze the evolution trends with varying geometry at different temperatures for important quantities in circuit design, such as the transconductance, the conductance, and the transconductance over drain current ratio of individual transistors.Secondly, we explore the low-temperature co-integration and the full on-chip integration of semiconductor quantum devices with classical electronics aimed at specific measurements down to the millikelvin range.We first focus on the sub-nanoampere current measurement of quantum dot devices by designing and characterizing a low-power transimpedance amplifier (TIA). The high-gain amplifier is successfully applied to measure the current across single- and double quantum-dot devices, respectively wire-bonded a few mm away or on-chip integrated a few micrometers-away. To further leverage the integration into the same substrate, we connected GHz-range voltage-controlled oscillators to one of the gates of the double dot in an attempt to observe discrete charge pumping in a fully-integrated device.Lastly, we tackled the measurement of the gate capacitance of single quantum devices by proposing a new measurement scheme making use of the cryogenic electronics capabilities as an alternative to the well-known reflectometry. By integrating a voltage-controlled current excitation and a voltage-sensing amplifier in the 200 MHz range, both in close proximity to the quantum device connected to an LC tank, the read-out circuitry of a variation in the device capacitance becomes a purely lumped-element system with impedance measurement of the resonant circuit without any wave propagation like in reflectometry. This approach increases simplicity and compactness of the measurement set-up. We even replace the bulky passive inductor used in reflectometry by an active inductor made of transistors and capacitors, offering improved scalability with a 3-orders of magnitude lower area for the same inductance. The resulting circuit successfully measured aF-capacitance variations of nanometric transistors at 4.2K revealing oscillatory quantum effects in the gate capacitance as a function of the gate and back-gate voltages.At the end of this dissertation, a picture is given with the challenges laying ahead related to circuit architecture and design for the ultimate goal of entering into the era of large-scale quantum processing.
Quantum computing promises an exponential speed-up of computation compared to what is nowadays achievable with classical computers. In this way, it enables the evaluation of more complex models and the breaching of current security algorithms. For the operation of a quantum system, many questions remain to be answered. Currently, there are several quantum technologies that promise to be both reliable and scalable, two features required for large scale quantum operations. Common to all technologies is the operating temperature that needs to be close to absolute zero, i.e. below 100 mK, to suppress environment noise and allow the quantum properties to become 'visible'. In order for any quantum processor to be operated, a so-called quantum-classical interface is required for the quantum bit (qubit) read-out and control. This interface consists of various electronic blocks, such as analog-to-digital converters, digital-to-analog converters, mixers, amplifiers and a digital controller. Especially the analog blocks require effort to meet the noise and stability constraints as not to disturb the very sensitive qubits and allow reading of the tiny signals. As the qubits live in extremely deep-cryogenic temperatures, long wires interface the cryogenic with the room temperature environment, where most of the electronics is situated. However, for a scalable system, heat injection becomes a serious problem, with many wires between 300 K and sub-Kelvin. Furthermore, such amount of interconnects is challenging to mechanically place in a dilution refrigerator. Therefore, in this work, we propose to implement the electronics not at room temperature, but at a temperature much closer to the qubits, for example at 4 K. This not only reduces significantly the wiring between room temperature and the qubits, but we can also benefit from lower electronic noise at such a temperature. The operation of conventional electronics almost 200°C below its normal temperature range is not trivial as device properties alter significantly and most circuits no longer operate as intended. In CMOS processes, the main technology in the integrated electronics world, the behaviour of the transistors, required for the implementation of any circuit, deviates considerably at low temperatures. The transistor's threshold voltage goes up, the mobility increases and the subthreshold slope becomes steeper, to name just a few of these deviations. Although there are improvements in performance, there are also some counter effects, and characterization of the transistors is needed to observe the changes. Once devices are characterized at such low temperatures, new models can be built and circuits can be simulated and adapted to operate properly at cryogenic temperatures. Luckily, there are various commercially available devices that can already withstand the chills of cold. We demonstrated various commercially available devices, such as a field-programmable gate array (FPGA) implemented in a 28 nm CMOS process, to be operating without major concerns at 4~K. Its properties alter only slightly, within 5 to 10%, and all tested circuit implementations, working at 300~K, also worked at 4 K. We combined both commercially available devices, that operate 200 K below their specified temperature range, with custom designed CMOS circuits to implement a cryogenic read-out platform for spin qubits. This system comprises amplifiers, an ADC, an FPGA, voltage regulators and a clock generator. It allows to amplify the tiny signal from the qubits and digitize it directly in the FPGA in order to process the data locally at 4~K. This system is one of the first systematic attempts at operating a part of the quantum-classical interface at cryogenic temperatures and forms the basis for future systems comprising the complete electronic interface for qubits to operate at such low temperatures. One of the main problems to tackle for cryogenic electronic systems is their power consumption. Power budgets are simply limited to roughly 1 or 2 Watts at 4 K and exponentially lower at deeper cryogenic temperatures, thus limiting the size of large-scale electronic systems. Our approach of combined commercial and custom circuits will have to be steadily replaced by a single (custom) technology that meets both power and scalability constraints. One of the best candidates is CMOS, a technology that the industry has relied upon for several decades and benefits from many optimizations thanks to Moore's law.
Quantum computing promises to revolutionize our lives, achieving unprecedented computational powers and unlocking new possibilities in drug discovery, chemical simulations and cryptography. The fundamental unit of computation of a quantum computer is the quantum bit (qubit). It can be implemented in a number of technologies, such as superconducting qubits, spin qubits, photonic systems, trapped ions and NV-centers. Solid-state superconducting qubits and spin qubits seem to be the most promising ones, as shown by the recent demonstration of quantum supremacy with a superconducting qubit processor. Such quantum processors, to operate in the quantum regime, require very low temperatures around 10 mK, and they are hence kept inside dilution fridges. The electronics required to read out and control such processors is typically realized by discrete components or bulky scientific instruments at room temperature wired into the dilution fridge. Such approach is only feasible until few (< 100) qubits are handled, but it is not scalable for million-qubit processors required for fault-tolerant operation. In this thesis, readout and control electronics is proposed to be integrated and operated directly at cryogenic temperatures, in close proximity with the qubits and potentially even co-integrated. CMOS technology is advocated for its scalability, compactness and low prototyping cost, to create a comprehensive cryo-CMOS class of fully-integrated transceivers to read out and control solid-state qubits. In particular, the thesis focuses on cryo-CMOS radio-frequency integrated circuits for the readout of silicon quantum computers, looking to integrate the whole readout system, from the quantum layer to the room temperature user interface. Cryogenic CMOS devices are explored first, to lay the foundations of integrated circuit design. The realization of quantum dots in standard CMOS technology is explored as a platform to realize solid-state qubit arrays, demonstrating functionality at 50 mK and good reproducibility. Moreover, the operation of integrated transistors at 50 mK and 4.2 K is explored to understand their basic cryogenic functionality, through characterization and modeling. Then also integrated passives, such as capacitors, inductors and transformers, are studied and modeled at cryogenic temperatures. Then, a fully-integrated readout platform spanning across all the blocks needed for dispersive readout is proposed. A fully-integrated matrix of quantum dots with radio-frequency gate-based readout capabilities is demonstrated along with time- and frequency-multiplexing. This quantum-classical circuit shows all the features for a scalable approach and is the core of the platform following it. A cryogenic CMOS circulator based on a new all-pass filter architecture is demonstrated, to be used as integrated replacement for current bulky counterparts; it allows power reduction, insertion loss and bandwidth enhancement with respect to state-of-the-art integrated circulators. The rest of the front-end is also explored with dedicated test multiplexers, a low noise-amplifier and an oscillator, that are finally merged in a single fully-integrated low-noise receiver with frequency synthesizer operating at 3.5 K for scalable multiplexed readout of silicon qubits. The platform presented in this thesis, across temperature boundaries, carries all the features required for future scalable silicon quantum computing platforms and could therefore form their core.
Quantum computers can provide exponential speedup in solving certain computational problems pertaining to drug discovery, cybersecurity, weather forecasting, etc. Although a quantum computer with just 50-qubits has been shown to surpass the computing power of the best supercomputers in specific applications, millions of qubits would be required for useful practical applications. One of the biggest obstacles in scaling from 50 qubits to millions of qubits is the interconnect bottleneck between solid-state qubits operating at 20 milliKelvin inside a dilution refrigerator and control electronics outside the dilution refrigerator connected via long coaxial cables. A 50-qubit processor requires hundreds of cables, digital to analog converters, mixers and amplifiers, clearly challenging the scalability of the system. The goal of this research is to build scalable quantum computers by operating CMOS control electronics inside the dilution refrigerator in proximity to quantum processors. The dissertation covers a broad aspect of cryogenic integrated circuit design spanning across devices, circuits and systems.
In recent years, quantum computers have emerged as a disruptive technology capable of solving problems currently intractable for classical systems. Computation is performed using qubits, which exploit quantum properties like superposition and entanglement, and requires them to operate at cryogenic temperatures. As a result, quantum computers are built around cryostats that reach temperatures as low as \qty{10}{\milli\kelvin}. However, to deliver a significant advantage over conventional approaches, quantum computers must increase their qubit count, improve qubit quality, and adopt more sophisticated control and readout architectures. The integration of more complex or improved cryogenic electronics inside the cryostat can enhance the scalability of these systems, and is the topic of this thesis. The primary technology platform used in this work is based on cryogenic InGaAs/InP high-electron-mobility transistors (HEMTs). One objective was the development of cryogenic circuits that enhance the scalability of spin-qubit quantum computers by enabling efficient signal delivery in control and readout paths. To this end, cryogenic multiplexers were demonstrated with threshold voltages as low as \qty{90}{\milli\volt}, subthreshold swing of \qty{5}{\milli\volt\per dec}, and on-off ratio of 107 at \qty{4}{\kelvin}. In addition, a charge-storage array was developed for the local generation of qubit bias signals, using an operation scheme based on pulse trains to program voltage levels on capacitors that can be placed in proximity to qubit gates. A second objective was the fabrication of HEMTs with enhanced performance for use in cryogenic low-noise amplifiers, which are critical for qubit readout. Studies were performed to characterize self-heating, an effect that limits transistor performance at cryogenic temperatures. Moreover HEMTs with improved characteristics were fabricated, which achieved exceptional values in state-of-the-art metrics, including fT= \qty{622}{\giga\hertz}, fMAX= \qty{733}{\giga\hertz}, and a noise indication factor IDS/gm= \qty{0.17}{\sqrt{\volt \cdot \milli\meter / \siemens}} at \qty{4}{\kelvin}. These results represent a new record for the combination of high-frequency and low-noise performance in a cryogenic HEMT. These results establish the InGaAs/InP HEMT technology as a promising platform for the development of cryogenic circuits, and demonstrate its versatility in addressing multiple applications requiring both single-device performance and integration at the circuit level.
A fault tolerant scalable quantum computer requires more than 1000 Qubits to perform real time state correction and to improve the Qubit coherence time. The dense wiring connections required between the quantum processor placed at a 100 mK temperature and the room temperature control and readout electronics serve as a limiting factor in this system. Qubit control and readout electronics operating at 4 K temperature, placed closer to a quantum processor inside the dilution refrigerator avoids the dense wiring connections to room temperature electronics, and hence, serve as a potential solution to realize a scalable quantum computer. However, with no CMOS process technology models available at cryogenic temperatures, the design of a fully integrated, ultra-low power Qubit control and readout electronics at a sub-1 mW power consumption proves to be extremely challenging. In recent years, there has been a huge rise in interest among the research communities to understand and solve the device and circuit level challenges at deep cryogenic temperatures. This paper presents an overview of the recently published active and passive device nonidealities, circuit design challenges and solutions, and the future research directions in the Qubit control and readout electronics operating at deep cryogenic temperatures.
Quantum computing has shown an increased interest in recent years. The basis of a quantum computer is a qubit, which is the quantum equivalent of a classical bit. Common qubit are only viable in a cryogenic environment and need electrical connections tooperate. For this, it is needed to solve the problem to bringing more qubits into the cryostat and connecting the quantum and the macroscopic world. The number of qubits per cryostat is limited just by the amount of interconnects and cooling power of the cryostat even if one neglect the other challenges which come with the increasing number of qubits integrated on one chip. This work investigates the performance of different integrated circuit architectures for operating at low temperature. The goal is to place the control electronics in close vicinity of the qubit itself and replace parts of the classical control electronics which by now are located at room temperature. The particular circuits investigated and implemented focus on the needs for operating a GaAs singlet triplet qubit. These qubits need frequency synthesis, biasing and readout circuitry to operate. This work includes the implementation of a digital controlled oscillator operating at a frequency of 500 MHz, a voltage controlled oscillator operating at 20 GHz and a 8-bit digital to analog converter with a sample rate of 250 MHz. The circuitry was fabricated on a 2 x 2 mm2 65 nm chip. The performance of the circuitry is evaluated at room temperature and in a closed-cycle Gifford-McMahon cryostat down to temperatures as low as 6 K. The results are compared and cryogenic effects are discussed