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Springer eBooks

Design of an Integrated Superconducting Qubit Chip

Hiu Yung Wong

Published Jan 1, 2025• 0 citations
Publisher
DOI
10.1007/978-3-031-78219-0_24

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As designs for superconducting qubits become more complex, 3D integration of two or more vertically bonded chips will become necessary to enable increased density and connectivity. Precise control of the spacing between these chips is required for accurate prediction of circuit performance. In this paper, we demonstrate an improvement in the planarity of bonded superconducting qubit chips while retaining device performance by utilizing hard-stop silicon spacer posts. These silicon spacers are defined by etching several microns into a silicon substrate and are compatible with 3D-integrated qubit fabrication. This includes fabrication of Josephson junctions, superconducting air-bridge crossovers, underbump metallization and indium bumps. To qualify the integrated process, we demonstrate high-quality factor resonators on the etched surface and measure qubit coherence (T1, T2,echo> 40 μs) in the presence of silicon posts as near as 350 μm to the qubit.

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InductEx [1] is a software tool used for the analysis of integrated circuit designs and extraction of design parameters by way of numerical electromagnetic field solving. This tool was originally developed with Rapid Single Flux Quantum (RSFQ) chips in mind, but it has a broad applicability and can be extended to other processes. In this poster, we report a comprehensive analysis of a superconducting aluminum two qubit chip. This analysis was performed with InductEx. We report the design of a two qubit chip which has the characteristics necessary to execute single and two qubit gates. Ahead of fabrication, several design characteristics have been extracted from this quantum chip design in order to verify that it satisfies basic design principles of transmon qubits. These characteristics are reported in this poster and they include the calculation of chip anharmonicities, qubit frequencies, resonator frequencies as well as g-factors and dispersive shifts. Design constraints which are satisfied by these extracted parameters are discussed. Additionally, qualitative aspects of the chip have been obtained from current density maps and are reported here. Taken as a whole, this analysis demonstrates the broad applicability of Inductex to integrated circuit design and particularly to the problem of quantum circuit layout optimization.
This paper proposes a scheme and design of cryogenic multiplexing control chip (MCC) which enables one microwave cable to control many superconducting qubits. Designed based on adjustable inductor, MCC is a non-reciprocal device which generates microwave signals between 4 and 8 GHz and constructs XY control circuit to operate qubits. The effects of filters, isolators, power splitters, qubits and load impedance on MCC are analyzed in the frequency-domain simulation. And in time-domain simulation, the response time, Gaussian pulses, single-sideband, amplitude and frequency compensation of MCC are examined. The MCC can be integrated with the superconducting qubits on the same package at 20 mK temperature stage, and output specific microwave pulses used to drive the superconducting qubits without crosstalks. The MCC can greatly reduce the number of microwave control lines and is beneficial to the development of large-scale superconducting quantum processor.
As designs for superconducting qubits become more complex, 3D integration of two or more vertically bonded chips will become necessary to enable increased density and connectivity. Precise control of the spacing between these chips is required for accurate prediction of circuit performance. In this paper, we demonstrate an improvement in the planarity of bonded superconducting qubit chips while retaining device performance by utilizing hard-stop silicon spacer posts. These silicon spacers are defined by etching several microns into a silicon substrate and are compatible with 3D-integrated qubit fabrication. This includes fabrication of Josephson junctions, superconducting air-bridge crossovers, underbump metallization and indium bumps. To qualify the integrated process, we demonstrate high-quality factor resonators on the etched surface and measure qubit coherence (T1, T2,echo> 40 μs) in the presence of silicon posts as near as 350 μm to the qubit.