A new class of quantum memory is proposed, termed the Superconducting Topological Memory State (STMS). In this framework the macroscopic phase of a superconducting condensate is not only determined by the instantaneous Hamiltonian but also encodes a history of the system's topological configuration. By coupling a superconducting circuit to a controllable topological transition, the condensate phase can lock into distinct metastable branches that are associated with different winding numbers of the superconducting order parameter. The memory is read out by measuring the persistent current or the Josephson phase across a weak link. The STMS exploits the inherent robustness of topological invariants and the dissipationless nature of superconductors to achieve long‑lived, non‑volatile quantum information. This manuscript develops the theoretical model, analyzes the dynamical conditions for memory formation, and discusses the potential for integration into hybrid quantum architectures. No experimental data are presented; the focus is on analytical and numerical insights that illuminate the feasibility and scalability of STMS as a novel quantum storage mechanism.A new class of quantum memory is proposed, termed the Superconducting Topological Memory State (STMS). In this framework the macroscopic phase of a superconducting condensate is not only determined by the instantaneous Hamiltonian but also encodes a history of the system's topological configuration. By coupling a superconducting circuit to a controllable topological transition, the condensate phase can lock into distinct metastable branches that are associated with different winding numbers of the superconducting order parameter. The memory is read out by measuring the persistent current or the Josephson phase across a weak link. The STMS exploits the inherent robustness of topological invariants and the dissipationless nature of superconductors to achieve long‑lived, non‑volatile quantum information. This manuscript develops the theoretical model, analyzes the dynamical conditions for memory formation, and discusses the potential for integration into hybrid quantum architectures. No experimental data are presented; the focus is on analytical and numerical insights that illuminate the feasibility and scalability of STMS as a novel quantum storage mechanism.

Aug 17, 20260 citations

Scalable Superconducting Nanowire Memory Array with Row-Column Addressing

Owen Medeiros, Matteo Castellani, Valentin Karam +6 more

Developing ultra-low-energy superconducting computing and fault-tolerant quantum computing will require scalable superconducting memory. While conventional superconducting logic-based memory cells have facilitated early demonstrations, their large footprint poses a significant barrier to scaling. Nanowire-based superconducting memory cells offer a compact alternative, but high error rates have hindered their integration into large arrays. In this work, we present a superconducting nanowire memory array designed for scalable row-column operation, achieving a functional density of 2.6 $\,$ Mb/cm $^{2}$ . The array operates at $1.3\,$ K, where we implement and characterize multi-flux quanta state storage and destructive readout. By optimizing write and read pulse sequences, we minimize bit errors while maximizing operational margins in a $4\times 4$ array. Circuit-level simulations further elucidate the memory cell's dynamics, providing insight into performance limits and stability under varying pulse amplitudes. We experimentally demonstrate stable memory operation with a minimum bit error rate of $10^{-5}$ . These results suggest a promising path for scaling superconducting nanowire memories to high-density architectures, offering a foundation for energy-efficient memory in superconducting electronics.Developing ultra-low-energy superconducting computing and fault-tolerant quantum computing will require scalable superconducting memory. While conventional superconducting logic-based memory cells have facilitated early demonstrations, their large footprint poses a significant barrier to scaling. Nanowire-based superconducting memory cells offer a compact alternative, but high error rates have hindered their integration into large arrays. In this work, we present a superconducting nanowire memory array designed for scalable row-column operation, achieving a functional density of 2.6$\,$Mb/cm$^{2}$. The array operates at $1.3\,$K, where we implement and characterize multi-flux quanta state storage and destructive readout. By optimizing write and read pulse sequences, we minimize bit errors while maximizing operational margins in a $4\times 4$ array. Circuit-level simulations further elucidate the memory cell's dynamics, providing insight into performance limits and stability under varying pulse amplitudes. We experimentally demonstrate stable memory operation with a minimum bit error rate of $10^{-5}$. These results suggest a promising path for scaling superconducting nanowire memories to high-density architectures, offering a foundation for energy-efficient memory in superconducting electronics.

arXiv:2503.22897Mar 28, 20251 citation

\,

Mb/cm

^{2}

. The array operates at

1.3\,

K, where we implement and characterize multi-flux quanta state storage and destructive readout. By optimizing write and read pulse sequences, we minimize bit errors while maximizing operational margins in a

4\times 4

array. Circuit-level simulations further elucidate the memory cell's dynamics, providing insight into performance limits and stability under varying pulse amplitudes. We experimentally demonstrate stable memory operation with a minimum bit error rate of

10^{-5}

. These results suggest a promising path for scaling superconducting nanowire memories to high-density architectures, offering a foundation for energy-efficient memory in superconducting electronics.