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arXiv:2005.14298 · Nature Communications

Preliminary demonstration of a persistent Josephson phase-slip memory cell with topological protection

Nadia Ligato, Elia Strambini, Federico Paolucci, Francesco Giazotto

Published Aug 31, 2021• 28 citations
arXivHTMLPDF

Abstract

Abstract Superconducting computing promises enhanced computational power in both classical and quantum approaches. Yet, efficient schemes for scalable and fast superconducting memories are still missing. On the one hand, the large inductance required in magnetic flux-controlled Josephson memories impedes device miniaturization and scalability. On the other hand, schemes based on the ferromagnetic order to store information often degrades superconductivity, and limits the operation speed to the magnetization switching rate of a few GHz. Here, we overcome these limitations with a fully superconducting memory cell based on the hysteretic phase-slip transition existing in long aluminum nanowire Josephson junctions. The memory logic state is codified in the topological index of the junction providing a robust protection against stocastic phase slips and magnetic flux noise. Our direct and non-destructive read-out schemes, based on local DC or AC tunneling spectroscopy, ensure reduced dissipation (≤ 40 fW) thereby yielding a very low energy per bit read-out power consumption as low as ~ 10-24 J as estimated from the typical time response of the structure (≤ 30 ps). The memory, measured over several days, showed no evidence of information degradation up to ~1.1 K, i.e., ~85% of the critical temperature of aluminum. The ease of operation combined with remarkable performance elects the Josephson phase-slip memory as an attractive storage cell to be exploited in advanced superconducting classical logic architectures or flux qubits.

DOI
10.1038/s41467-021-25209-y

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Abstract Superconducting computing promises enhanced computational power in both classical and quantum approaches. Yet, efficient schemes for scalable and fast superconducting memories are still missing. On the one hand, the large inductance required in magnetic flux-controlled Josephson memories impedes device miniaturization and scalability. On the other hand, schemes based on the ferromagnetic order to store information often degrades superconductivity, and limits the operation speed to the magnetization switching rate of a few GHz. Here, we overcome these limitations with a fully superconducting memory cell based on the hysteretic phase-slip transition existing in long aluminum nanowire Josephson junctions. The memory logic state is codified in the topological index of the junction providing a robust protection against stocastic phase slips and magnetic flux noise. Our direct and non-destructive read-out schemes, based on local DC or AC tunneling spectroscopy, ensure reduced dissipation (≤ 40 fW) thereby yielding a very low energy per bit read-out power consumption as low as ~ 10-24 J as estimated from the typical time response of the structure (≤ 30 ps). The memory, measured over several days, showed no evidence of information degradation up to ~1.1 K, i.e., ~85% of the critical temperature of aluminum. The ease of operation combined with remarkable performance elects the Josephson phase-slip memory as an attractive storage cell to be exploited in advanced superconducting classical logic architectures or flux qubits.
Abstract Superconducting computing promises enhanced computational power in both classical and quantum approaches. Yet, scalable and fast superconducting memories are not implemented. Here, we propose a fully superconducting memory cell based on the hysteretic phase-slip transition existing in long aluminum nanowire Josephson junctions. Embraced by a superconducting ring, the memory cell codifies the logic state in the direction of the circulating persistent current, as commonly defined in flux-based superconducting memories. But, unlike the latter, the hysteresis here is a consequence of the phase-slip occurring in the long weak link and associated to the topological transition of its superconducting gap. This disentangles our memory scheme from the large-inductance constraint, thus enabling its miniaturization. Moreover, the strong activation energy for phase-slip nucleation provides a robust topological protection against stochastic phase-slips and magnetic-flux noise. These properties make the Josephson phase-slip memory a promising solution for advanced superconducting classical logic architectures or flux qubits.
Abstract A superconducting loop stores persistent current without any ohmic loss, making it an ideal platform for energy efficient memories. Conventional superconducting memories use an architecture based on Josephson junctions (JJs) and have demonstrated access times less than 10 ps and power dissipation as low as 10 −19 J. However, their scalability has been slow to develop due to the challenges in reducing the dimensions of JJs and minimizing the area of the superconducting loops. In addition to the memory itself, complex readout circuits require additional JJs and inductors for coupling signals, increasing the overall area. Here, we have demonstrated a superconducting memory based solely on lithographic nanowires. The small dimensions of the nanowire ensure that the device can be fabricated in a dense area in multiple layers, while the high kinetic inductance makes the loop essentially independent of geometric inductance, allowing it to be scaled down without sacrificing performance. The memory is operated by a group of nanowire cryotrons patterned alongside the storage loop, enabling us to reduce the entire memory cell to 3 μ m × 7 μ m in our proof-of-concept device. In this work we present the operation principles of a superconducting nanowire memory (nMem) and characterize its bit error rate, speed, and power dissipation.
A superconducting loop stores persistent current without any ohmic loss, making it an ideal platform for energy efficient memories. Conventional superconducting memories use an architecture based on Josephson junctions (JJs) and have demonstrated access times less than 10 ps and power dissipation as low as 10[superscript -19] J. However, their scalability has been slow to develop due to the challenges in reducing the dimensions of JJs and minimizing the area of the superconducting loops. In addition to the memory itself, complex readout circuits require additional JJs and inductors for coupling signals, increasing the overall area. Here, we have demonstrated a superconducting memory based solely on lithographic nanowires. The small dimensions of the nanowire ensure that the device can be fabricated in a dense area in multiple layers, while the high kinetic inductance makes the loop essentially independent of geometric inductance, allowing it to be scaled down without sacrificing performance. The memory is operated by a group of nanowire cryotrons patterned alongside the storage loop, enabling us to reduce the entire memory cell to 3 μm ×7 μm in our proof-of-concept device. In this work we present the operation principles of a superconducting nanowire memory (nMem) and characterize its bit error rate, speed, and power dissipation.
The talk is based on an overview which was published recently (1). For this reason, only an abstract is given here, which includes Later results not contained in the aforementioned overview. The presently-known Josephson memory cells store information as persistent currents in superconducting loops, or what is equivalent as a magnetic flux in the area of the ring. This method of storage is nonvolatile and has no power consumption in the storing state. In a superconducting ring system, the magnetic flux is quantized, and cells have been built which operate either with only one flux quantum, or with many of them. For the Latter cells with many flux quanta (ring cells), quite a number of designs exist. They have one or two Josephson junctions in the ring, which allow writing. An external junction which is controlled by the ring current serves for non-destructive reading of the information. The smallest cell realized had an area of 900 ?m2 with a 2 ?m minimum line width. Switching speed was ? 80 ps. Cells which store information as a single-flux quantum (single flux-quantum cells = SFQ cells) in the ring, usually contain two Josephson junctions used for reading and writing. Read-out in most of these cells is destructive, but methods of reading non-destructively have also been proposed. The smallest device made had an area of ? 150 ?m2 with a minimum line width of 2 ?m. The read signal had a rise time ? 100 ps.
Abstract The ongoing progress of superconducting logic systems with Josephson junctions as base elements requires the development of compatible cryogenic memory. Long enough junctions subject to magnetic field host quantum phase 2 π -singularities—Josephson vortices. Here, we report the realization of the superconducting memory cell whose state is encoded by the number of present Josephson vortices. By integrating the junction into a coplanar resonator and by applying a microwave excitation well below the critical current, we are able to control the state of the system in an energy-efficient and non-destructive manner. The memory effect arises due to the presence of the natural edge barrier for Josephson vortices. The performance of the device is evaluated, and the routes for creating scalable cryogenic memories directly compatible with superconducting microwave technologies are discussed.
Developing ultra-low-energy superconducting computing and fault-tolerant quantum computing will require scalable superconducting memory. While conventional superconducting logic-based memory cells have facilitated early demonstrations, their large footprint poses a significant barrier to scaling. Nanowire-based superconducting memory cells offer a compact alternative, but high error rates have hindered their integration into large arrays. In this work, we present a superconducting nanowire memory array designed for scalable row-column operation, achieving a functional density of 2.6 \,Mb/cm2^{2}2. The array operates at 1.3 1.3\,1.3K, where we implement and characterize multi-flux quanta state storage and destructive readout. By optimizing write and read pulse sequences, we minimize bit errors while maximizing operational margins in a 4×44\times 44×4 array. Circuit-level simulations further elucidate the memory cell's dynamics, providing insight into performance limits and stability under varying pulse amplitudes. We experimentally demonstrate stable memory operation with a minimum bit error rate of 10−510^{-5}10−5. These results suggest a promising path for scaling superconducting nanowire memories to high-density architectures, offering a foundation for energy-efficient memory in superconducting electronics.