Quantum computing is a new paradigm of computation that exploits principles from quantum mechanics to achieve an exponential speedup compared to classical logic. However, noise strongly limits current quantum hardware, reducing achievable performance and limiting the scaling of the applications. For this reason, current noisy intermediate-scale quantum devices require Quantum Error Correction (QEC) mechanisms to identify errors occurring in the computation and correct them in real time. Nevertheless, the high computational complexity of QEC algorithms is incompatible with the tight time constraints of quantum devices. Thus, hardware acceleration is paramount to achieving real-time QEC. This work presents QASBA, an FPGA-based hardware accelerator for the Sparse Blossom Algorithm (SBA), a state-of-the-art decoding algorithm. After profiling the state-of-the-art software counterpart, we developed a design methodology for hardware development based on the SBA. We also devised an automation process to help users without expertise in hardware design in deploying architectures based on QASBA. We implement QASBA on different FPGA architectures and experimentally evaluate resource usage, execution time, and energy efficiency of our solution. Our solution attains up to \(25.05\times\) speedup and \(304.16\times\) improvement in energy efficiency compared to the software baseline.
Quantum computing is a new paradigm of computation that exploits principles from quantum mechanics to achieve an exponential speedup compared to classical logic. However, noise strongly limits current quantum hardware, reducing achievable performance and limiting the scaling of the applications. For this reason, current noisy intermediate-scale quantum devices require Quantum Error Correction (QEC) mechanisms to identify errors occurring in the computation and correct them in real time. Nevertheless, the high computational complexity of QEC algorithms is incompatible with the tight time constraints of quantum devices. Thus, hardware acceleration is paramount to achieving real-time QEC. This work presents QASBA, an FPGA-based hardware accelerator for the Sparse Blossom Algorithm (SBA), a state-of-the-art decoding algorithm. After profiling the state-of-the-art software counterpart, we developed a design methodology for hardware development based on the SBA. We also devised an automation process to help users without expertise in hardware design in deploying architectures based on QASBA. We implement QASBA on different FPGA architectures and experimentally evaluate resource usage, execution time, and energy efficiency of our solution. Our solution attains up to (25.05\times) speedup and (304.16\times) improvement in energy efficiency compared to the software baseline.
Quantum computing is a new computing paradigm that exploits laws of quantum mechanics to achieve an exponential speedup compared to classical logic. However, noise strongly limits current quantum hardware, reducing achievable performance. Quantum Error Correction (QEC) techniques are a valuable approach to reduce the effects of noise. Nevertheless, the high computational complexity of QEC algorithms is incompatible with the tight time constraints of quantum devices. Thus, hardware acceleration is paramount to achieving real-time QEC. This work represents the first step in the FPGA acceleration of the Sparse Blossom Algorithm (SBA), a state-of-the-art decoding algorithm for QEC. We provide a performance profiling and a design methodology for the hardware development of the SBA. We evaluate the execution time, and energy efficiency of our solution, attaining up to 2.75× speedup and 9.59× improvement in energy efficiency compared to the software baseline.
Current generation of Noisy Intermediate-Scale Quantum devices is mainly limited by noise, thus making Quantum Error Correction (QEC) mechanisms of paramount importance. QEC is carried out through classical computing architectures, and Field Programmable Gate Arrays (FPGAs) represent a promising platform on which deploying decoding algorithms. Nevertheless, accelerating QEC with FPGAs is a largely unexplored topic in the State of the Art, making it urgent to clearly define the requirements that these designs must satisfy. For this reason, in this work, we analyze literature solutions for FPGA-based QEC and identify the mandatory Key Performance Indicators (KPIs) to address when developing FPGA designs for this task. These KPIs are crucial to guide future research and unleash the full computing power of quantum devices.
Quantum computing represents an exciting computing paradigm that promises to solve problems untractable for a classical computer. The main limiting factor for quantum devices is the noise impacting qubits, which hinders the superpolynomial speedup promise. Thus, although Quantum Error Correction (QEC) mechanisms are paramount, QEC demands high speed and low latency to scale quantum computations to real-life-sized problems. Within this context, hardware accelerators, such as Field Programmable Gate Arrays (FPGAs), represent a valuable approach to fulfilling QEC requirements. Nevertheless, the literature falls short in proposing solutions targeting the toric code, a type of quantum Low-Density Parity Check code capable of encoding two logical qubits, thus requiring fewer physical qubits. This manuscript presents QUEKUF , an FPGA-based QEC dataflow architecture dealing with the toric code. QUEKUF disposes of parallel processing units to spatially parallelize QEC, which a centralized controller orchestrates for data movement and operation decisions. We also provide a latency-oriented resource optimization model to identify the best theoretical configuration of QUEKUF that minimizes latency and optimizes resource requirements based upon high-level quantum parameters. Experimental results show that QUEKUF attains up to 7.30× speedup and 81.51× improvement in energy efficiency over a C++ implementation with error-free syndromes while keeping high accuracy.
Quantum computers are growing at a rapid pace. Trends show that the current decade could be the one in which quantum computers deliver commercial value. Today's quantum computers are overwhelmed by errors. To unlock their massive potential, a significant reduction in errors is required. Several qubit technologies are under research, e.g. superconducting, neutral atoms, trapped ions, photons and silicon. For useful quantum computing on these qubit technologies, Quantum Error Correction (QEC) turns unreliable physical qubits into useful logical qubits. QEC requires solving a real-time, large data volume decoding problem that determines the effect of physical noise on the computation carried out on logical qubits. The nature of the decoding problem depends on the qubit technology, choice of QEC code and mode of quantum computation. These are actively researched subjects in the quantum computing world. Hardware-based decoders that use Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuits (ASIC) technologies are the most promising solutions in terms of speed and scalability. However, the design methodology for these solutions typically suffers from long lead times and a lack of flexibility. We propose GridGenQ, a hardware design utility that automates part of the FPGA/ASIC design methodology for distributed QEC decoders. We show that with our novel solution, development time for such distributed hardware decoders can be reduced from several weeks to few minutes. This allows for fast prototyping of distributed decoder architectures to meet the requirements posed by a dynamic QEC landscape.
Quantum computers can solve selected problems more efficiently than classical computers, but current devices are limited by high physical error rates. Quantum Error Correction (QEC) mitigates this by encoding many physical qubits into a logical qubit, with the surface code among the most widely studied approaches. Since syndrome measurements are produced continuously, the decoder must process them fast enough to avoid becoming a system bottleneck, making real-time decoding essential for fault-tolerant quantum computing. While most state-of-the-art real-time decoders rely on Minimum-Weight Perfect Matching (MWPM), we instead use a high-accuracy Graph Neural Network (GNN) that trades higher computational cost for lower logical error rates. To make this GNN practical for real-time decoding, we apply algorithm-hardware co-design. We reduce complexity through hardware-guided pruning and retraining, producing two hardware-friendly models that reduce parameter count by 3.1× and 6.5×. These target, respectively, an average decoding latency of one syndrome cycle and a worst-case latency within one syndrome cycle. We further reduce hardware cost using input-graph filtering and post-training quantization. Based on these optimized models, we propose an FPGA-based architecture for low-latency inference and real-time decoding. Evaluated on surface codes up to distance 7 under circuit-level noise at physical error rate p=10−3, our decoder outperforms MWPM in decoding accuracy for both average-latency and max-latency settings. It reduces logical error rate by 40% at 1μs average latency, and by 13% under a strict 1μs deadline.
As quantum computing moves toward fault-tolerant architectures, quantum error correction (QEC) decoder performance is increasingly critical for scalability. Understanding the impact of transitioning from floating-point software to finite-precision hardware is essential, as hardware decoder performance affects code distance, qubit requirements, and connectivity between quantum and classical control units. This paper introduces a hardware emulator to evaluate QEC decoders using real hardware instead of software models. The emulator can explore 10 13 different error patterns in 20 days with a single FPGA device running at 150 MHz, guaranteeing the decoder's performance at logical rates of 10 − 12 , the requirement for most quantum algorithms. In contrast, an optimized C++ software on an Intel Core i9 with 128 GB RAM would take over a year to achieve similar results. The emulator also enables the storage of uncorrectable error patterns that generate logical errors, allowing for offline analysis and the design of new decoders. Using results from the emulator, we propose a method that combines several belief propagation (BP) decoders with different quantization levels, which we define as a diversity-based decoder. Individually, these decoders may show subpar error correction, but together they outperform the floating-point version of BP for quantum low-density parity-check (QLDPC) codes like hypergraph or lifted product. Preliminary results with circuit-level noise and bivariate bicycle codes suggest that hardware insights can also improve software. Our diversity-based proposal achieves a similar logical error rate as the well-known approach, BP with ordered statistics (BP+OSD) decoding, with average speed improvements ranging from 30% to 80%, and 10% to 120% in worst-case scenarios, while reducing post-processing algorithm activation from 47% to 96.93%, maintaining the same accuracy.