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IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum

Towards the Acceleration of the Sparse Blossom Algorithm for Quantum Error Correction

M. Vénere, Valentino Guerrini, Beatrice Branchini, Davide Conficconi, Donatella Sciuto, Marco Domenico Santambrogio

Published May 27, 2024• 2 citations
Publisher

Abstract

Quantum computing is a new computing paradigm that exploits laws of quantum mechanics to achieve an exponential speedup compared to classical logic. However, noise strongly limits current quantum hardware, reducing achievable performance. Quantum Error Correction (QEC) techniques are a valuable approach to reduce the effects of noise. Nevertheless, the high computational complexity of QEC algorithms is incompatible with the tight time constraints of quantum devices. Thus, hardware acceleration is paramount to achieving real-time QEC. This work represents the first step in the FPGA acceleration of the Sparse Blossom Algorithm (SBA), a state-of-the-art decoding algorithm for QEC. We provide a performance profiling and a design methodology for the hardware development of the SBA. We evaluate the execution time, and energy efficiency of our solution, attaining up to 2.75× speedup and 9.59× improvement in energy efficiency compared to the software baseline.

DOI
10.1109/ipdpsw63119.2024.00033

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Quantum computing is a new computing paradigm that exploits laws of quantum mechanics to achieve an exponential speedup compared to classical logic. However, noise strongly limits current quantum hardware, reducing achievable performance. Quantum Error Correction (QEC) techniques are a valuable approach to reduce the effects of noise. Nevertheless, the high computational complexity of QEC algorithms is incompatible with the tight time constraints of quantum devices. Thus, hardware acceleration is paramount to achieving real-time QEC. This work represents the first step in the FPGA acceleration of the Sparse Blossom Algorithm (SBA), a state-of-the-art decoding algorithm for QEC. We provide a performance profiling and a design methodology for the hardware development of the SBA. We evaluate the execution time, and energy efficiency of our solution, attaining up to 2.75× speedup and 9.59× improvement in energy efficiency compared to the software baseline.
Quantum computing is a new paradigm of computation that exploits principles from quantum mechanics to achieve an exponential speedup compared to classical logic. However, noise strongly limits current quantum hardware, reducing achievable performance and limiting the scaling of the applications. For this reason, current noisy intermediate-scale quantum devices require Quantum Error Correction (QEC) mechanisms to identify errors occurring in the computation and correct them in real time. Nevertheless, the high computational complexity of QEC algorithms is incompatible with the tight time constraints of quantum devices. Thus, hardware acceleration is paramount to achieving real-time QEC. This work presents QASBA, an FPGA-based hardware accelerator for the Sparse Blossom Algorithm (SBA), a state-of-the-art decoding algorithm. After profiling the state-of-the-art software counterpart, we developed a design methodology for hardware development based on the SBA. We also devised an automation process to help users without expertise in hardware design in deploying architectures based on QASBA. We implement QASBA on different FPGA architectures and experimentally evaluate resource usage, execution time, and energy efficiency of our solution. Our solution attains up to 25.05×25.05\times25.05× speedup and 304.16×304.16\times304.16× improvement in energy efficiency compared to the software baseline.
Current generation of Noisy Intermediate-Scale Quantum devices is mainly limited by noise, thus making Quantum Error Correction (QEC) mechanisms of paramount importance. QEC is carried out through classical computing architectures, and Field Programmable Gate Arrays (FPGAs) represent a promising platform on which deploying decoding algorithms. Nevertheless, accelerating QEC with FPGAs is a largely unexplored topic in the State of the Art, making it urgent to clearly define the requirements that these designs must satisfy. For this reason, in this work, we analyze literature solutions for FPGA-based QEC and identify the mandatory Key Performance Indicators (KPIs) to address when developing FPGA designs for this task. These KPIs are crucial to guide future research and unleash the full computing power of quantum devices.
This paper investigates the potential of leveraging quantum error correction (QEC) codes within a hardware-accelerated quantum computing architecture. The core claim centers around designing a system that utilizes the inherent error-correcting capabilities of QEC codes to dramatically improve the robustness and computational efficiency of quantum computations. The proposed mechanism involves tightly integrating specific QEC codes with tailored hardware designs, employing hardware acceleration techniques to expedite the computationally intensive error correction encoding and decoding processes. The novelty lies in translating the theoretical advantages of QEC codes into tangible hardware acceleration benefits, thereby significantly enhancing the practicality and scalability of quantum computing. We explore the fundamental principles, architectural considerations, and potential performance gains associated with this approach, focusing on the reduction of logical qubit decoherence and the optimization of quantum gate operations. This work provides a framework for future research and development in building fault-tolerant quantum computers.
Quantum Error Correction (QEC) is essential for building robust, fault-tolerant quantum computers; however, the decoding process often presents a significant computational bottleneck. Tesseract is a novel Most-Likely-Error (MLE) decoder for QEC that employs the A* search algorithm to explore an exponentially large graph of error hypotheses, achieving high decoding speed and accuracy. This paper presents a systematic approach to optimizing the Tesseract decoder through low-level performance enhancements. Based on extensive profiling, we implemented four targeted optimization strategies, including the replacement of inefficient data structures, reorganization of memory layouts to improve cache hit rates, and the use of hardware-accelerated bit-wise operations. We achieved significant decoding speedups across a wide range of code families and configurations, including Color Codes, Bivariate-Bicycle Codes, Surface Codes, and Transversal CNOT Protocols. Our results demonstrate consistent speedups of approximately 2x for most code families, often exceeding 2.5x. Notably, we achieved a peak performance gain of over 5x for the most computationally demanding configurations of Bivariate-Bicycle Codes. These improvements make the Tesseract decoder more efficient and scalable, serving as a practical case study that highlights the importance of high-performance software engineering in QEC and providing a strong foundation for future research.
Quantum Error Correction (QEC) is required in quantum computers to mitigate the effect of errors on physical qubits. When adopting a QEC scheme based on surface codes, error decoding is the most computationally expensive task in the classical electronic back-end. Decoders employing neural networks (NN) are well-suited for this task but their hardware implementation has not been presented yet. This work presents a space exploration of fully-connected feed-forward NN decoders for small distance surface codes. The goal is to optimize the neural network for high decoding performance, while keeping a minimalistic hardware implementation. This is needed to meet the tight delay constraints of real-time surface code decoding. We demonstrate that hardware based NN-decoders can achieve high decoding performance comparable to other state-of-the-art decoding algorithms whilst being well below the tight delay requirements (440 ns) of current solid-state qubit technologies for both ASIC designs (<30 ns) and FPGA implementations (<90 ns). These results indicate that NN-decoders are viable candidates for further exploration of an integrated hardware implementation in future large-scale quantum computers.
Quantum computers can solve selected problems more efficiently than classical computers, but current devices are limited by high physical error rates. Quantum Error Correction (QEC) mitigates this by encoding many physical qubits into a logical qubit, with the surface code among the most widely studied approaches. Since syndrome measurements are produced continuously, the decoder must process them fast enough to avoid becoming a system bottleneck, making real-time decoding essential for fault-tolerant quantum computing. While most state-of-the-art real-time decoders rely on Minimum-Weight Perfect Matching (MWPM), we instead use a high-accuracy Graph Neural Network (GNN) that trades higher computational cost for lower logical error rates. To make this GNN practical for real-time decoding, we apply algorithm-hardware co-design. We reduce complexity through hardware-guided pruning and retraining, producing two hardware-friendly models that reduce parameter count by 3.1×3.1\times3.1× and 6.5×6.5\times6.5×. These target, respectively, an average decoding latency of one syndrome cycle and a worst-case latency within one syndrome cycle. We further reduce hardware cost using input-graph filtering and post-training quantization. Based on these optimized models, we propose an FPGA-based architecture for low-latency inference and real-time decoding. Evaluated on surface codes up to distance 7 under circuit-level noise at physical error rate p=10−3p=10^{-3}p=10−3, our decoder outperforms MWPM in decoding accuracy for both average-latency and max-latency settings. It reduces logical error rate by 40% at 1μs1μs1μs average latency, and by 13% under a strict 1μs1μs1μs deadline.