For scalable semiconductor-based quantum computer, integration of qubit, electrometer and readout circuit on CMOS platform needs to be explored. Here, for qubit readout, the use of charge-based capacitance measurement (CBCM) is proposed to detect the atto-farad change in the gate input capacitance of single-electron transistor (SET) electrometer. Mixed SET-CMOS circuit simulation revealed that a few hundred microvolts signal appeared at the integration capacitance at 1MHz data rate and the gate capacitance profile with respect to the gate voltage was successfully reproduced.
For scalable semiconductor-based quantum computer, integration of qubit, electrometer and readout circuit on CMOS platform needs to be explored. Here, for qubit readout, the use of charge-based capacitance measurement (CBCM) is proposed to detect the atto-farad change in the gate input capacitance of single-electron transistor (SET) electrometer. Mixed SET-CMOS circuit simulation revealed that a few hundred microvolts signal appeared at the integration capacitance at 1MHz data rate and the gate capacitance profile with respect to the gate voltage was successfully reproduced.
Quantum computation requires a qubit-specific measurement capability to read out the final states of individual qubits. Promising semiconductor architectures use external readout electrometers, but these could be replaced by more scalable $g\phantom{\rule{0}{0ex}}a\phantom{\rule{0}{0ex}}t\phantom{\rule{0}{0ex}}e$ $s\phantom{\rule{0}{0ex}}e\phantom{\rule{0}{0ex}}n\phantom{\rule{0}{0ex}}s\phantom{\rule{0}{0ex}}o\phantom{\rule{0}{0ex}}r\phantom{\rule{0}{0ex}}s$, based on the dispersive coupling between an electrical resonator and the qubit. The authors present an optimized gate sensor and show that significantly better sensitivity arises from changing circuit topology to enhance the resonator's Q factor. Here CMOS-based quantum devices achieve charge sensitivity on par with that of the best single-electron electrometers.
In the pursuit for scalable quantum processors, significant effort is being devoted to the development of cryogenic classical hardware for the control and readout of a growing number of qubits. In this manuscript, we present a novel approach called impedancemetry that is suitable for measuring the quantum capacitance of semiconductor qubits connected to a resonant LC-circuit. The impedancemetry circuit exploits the integration of a CMOS-based active inductor in the resonator with tunable resonance frequency and quality factor, enabling optimization of readout sensitivity for quantum devices. The realized cryogenic circuit allows fast impedance detection with a measured capacitance resolution down to 10 aF and an input-referred noise of 3.7 aF/Hz. At 4.2 K, the power consumption of the active inductor amounts to 120 μW, with an additional dissipation for on-chip current excitation (0.15 μW) and voltage amplification (2.9 mW) of the impedance measurement. Compared to commonly used schemes based on dispersive RF reflectometry which require mm-scale passive inductors, the circuit has a notably reduced footprint (50 μm × 60 μm), facilitating its integration in a scalable quantum-classical architecture. The impedancemetry method has been applied at 4.2 K to the detection of quantum effects in the gate capacitance of on-chip nanometric CMOS transistors that are individually addressed via multiplexing.
The readout of a solid state qubit often relies on single charge sensitive electrometry. However the combination of fast and accurate measurements is non trivial due to large RC time constants due to the electrometers resistance and shunt capacitance from wires between the cold stage and room temperature. Currently fast sensitive measurements are accomplished through rf reflectrometry. I will present an alternative single charge readout technique based on cryogenic CMOS circuits in hopes to improve speed, signal-to-noise, power consumption and simplicity in implementation. The readout circuit is based on a current comparator where changes in current from an electrometer will trigger a digital output. These circuits were fabricated using Sandia's 0.35 {micro}m CMOS foundry process. Initial measurements of comparators with an addition a current amplifier have displayed current sensitivities of < 1nA at 4.2K, switching speeds up to {approx}120ns, while consuming {approx}10 {micro}W. I will also discuss an investigation of noise characterization of our CMOS process in hopes to obtain a better understanding of the ultimate limit in signal to noise performance.
Quantum computing promises to revolutionize our lives, achieving unprecedented computational powers and unlocking new possibilities in drug discovery, chemical simulations and cryptography. The fundamental unit of computation of a quantum computer is the quantum bit (qubit). It can be implemented in a number of technologies, such as superconducting qubits, spin qubits, photonic systems, trapped ions and NV-centers. Solid-state superconducting qubits and spin qubits seem to be the most promising ones, as shown by the recent demonstration of quantum supremacy with a superconducting qubit processor. Such quantum processors, to operate in the quantum regime, require very low temperatures around 10 mK, and they are hence kept inside dilution fridges. The electronics required to read out and control such processors is typically realized by discrete components or bulky scientific instruments at room temperature wired into the dilution fridge. Such approach is only feasible until few (< 100) qubits are handled, but it is not scalable for million-qubit processors required for fault-tolerant operation. In this thesis, readout and control electronics is proposed to be integrated and operated directly at cryogenic temperatures, in close proximity with the qubits and potentially even co-integrated. CMOS technology is advocated for its scalability, compactness and low prototyping cost, to create a comprehensive cryo-CMOS class of fully-integrated transceivers to read out and control solid-state qubits. In particular, the thesis focuses on cryo-CMOS radio-frequency integrated circuits for the readout of silicon quantum computers, looking to integrate the whole readout system, from the quantum layer to the room temperature user interface. Cryogenic CMOS devices are explored first, to lay the foundations of integrated circuit design. The realization of quantum dots in standard CMOS technology is explored as a platform to realize solid-state qubit arrays, demonstrating functionality at 50 mK and good reproducibility. Moreover, the operation of integrated transistors at 50 mK and 4.2 K is explored to understand their basic cryogenic functionality, through characterization and modeling. Then also integrated passives, such as capacitors, inductors and transformers, are studied and modeled at cryogenic temperatures. Then, a fully-integrated readout platform spanning across all the blocks needed for dispersive readout is proposed. A fully-integrated matrix of quantum dots with radio-frequency gate-based readout capabilities is demonstrated along with time- and frequency-multiplexing. This quantum-classical circuit shows all the features for a scalable approach and is the core of the platform following it. A cryogenic CMOS circulator based on a new all-pass filter architecture is demonstrated, to be used as integrated replacement for current bulky counterparts; it allows power reduction, insertion loss and bandwidth enhancement with respect to state-of-the-art integrated circulators. The rest of the front-end is also explored with dedicated test multiplexers, a low noise-amplifier and an oscillator, that are finally merged in a single fully-integrated low-noise receiver with frequency synthesizer operating at 3.5 K for scalable multiplexed readout of silicon qubits. The platform presented in this thesis, across temperature boundaries, carries all the features required for future scalable silicon quantum computing platforms and could therefore form their core.
A systematic research on the development of cryogenic complementary metal-oxide semiconductor (cryo-CMOS) circuits, for implementing the required control electronics to manipulate the quantum bit (qubit) state, is performed over the last few years. Scalability constitutes a key term regarding the evolution of quantum computing from theory to practical application and CMOS technology has been proven to be a promising candidate for implementing the coveted scalable next-generation quantum computers (QCs). Mixed-signal blocks, used for uniting the analog and digital domains, play a key role in the efficient functionality of the qubit control/readout system, thus there is an ever-increasing interest in their high-performance circuit realization. The critical challenge in this venture is to achieve efficient cryogenic operation at low temperatures, i.e., close to the qubit around 4 K, simultaneously keeping power requirements at low values. An overview and comparison of the cryo-CMOS Digital-to-Analog converter (DAC) and Analog-to-Digital converter (ADC) circuit implementations for quantum computing applications that heretofore have been proposed in the literature is presented in this work. A discussion on the challenges and future strategic steps that are henceforth required to proceed toward the development of a functional scalable quantum computer is also conducted.
Compact and scalable quantum computer required physical qubits with low footprint and cryogenic electronics to be used in situ as standard control/readout system. The small spatial gap between the quantum chip and the cryogenic electronics limits the complexity of the wiring connections and the associated stray capacitance of the wires themselves, yielding a gain in terms of bandwidth and resolution. These improvements allow to design a fully-integrated CMOS readout based on current measurements with similar performances compared to the most common RF reflectometry-based readout technique. Here, we propose an acquisition system, operating at 4.2 K, which converts the spin dependent current coming from a single-electron transistor charge sensor into a digital output with a small power consumption (1 mW/qubit) and small occupation area (2). The system on chip consists of a low noise active integrator for the spin current, feeding a programmable threshold comparator to provide a digital output of the qubit state. It exhibits a resolution of tens of pA over an average input current of 1 nA with a time resolution of 1 μs.Compared to spin-qubit readout based on RF-reflectometry techniques, our solution does not require bulky off-chip compo-nents and to handle microwave signal and fast analog-to digital converters.