In the pursuit for scalable quantum processors, significant effort is being devoted to the development of cryogenic classical hardware for the control and readout of a growing number of qubits. In this manuscript, we present a novel approach called impedancemetry that is suitable for measuring the quantum capacitance of semiconductor qubits connected to a resonant LC-circuit. The impedancemetry circuit exploits the integration of a CMOS-based active inductor in the resonator with tunable resonance frequency and quality factor, enabling optimization of readout sensitivity for quantum devices. The realized cryogenic circuit allows fast impedance detection with a measured capacitance resolution down to 10 aF and an input-referred noise of 3.7 aF/Hz. At 4.2 K, the power consumption of the active inductor amounts to 120 μW, with an additional dissipation for on-chip current excitation (0.15 μW) and voltage amplification (2.9 mW) of the impedance measurement. Compared to commonly used schemes based on dispersive RF reflectometry which require mm-scale passive inductors, the circuit has a notably reduced footprint (50 μm × 60 μm), facilitating its integration in a scalable quantum-classical architecture. The impedancemetry method has been applied at 4.2 K to the detection of quantum effects in the gate capacitance of on-chip nanometric CMOS transistors that are individually addressed via multiplexing.
In the pursuit for scalable quantum processors, significant effort is being devoted to the development of cryogenic classical hardware for the control and readout of a growing number of qubits. In this manuscript, we present a novel approach called impedancemetry that is suitable for measuring the quantum capacitance of semiconductor qubits connected to a resonant LC-circuit. The impedancemetry circuit exploits the integration of a CMOS-based active inductor in the resonator with tunable resonance frequency and quality factor, enabling optimization of readout sensitivity for quantum devices. The realized cryogenic circuit allows fast impedance detection with a measured capacitance resolution down to 10 aF and an input-referred noise of 3.7 aF/Hz. At 4.2 K, the power consumption of the active inductor amounts to 120 μW, with an additional dissipation for on-chip current excitation (0.15 μW) and voltage amplification (2.9 mW) of the impedance measurement. Compared to commonly used schemes based on dispersive RF reflectometry which require mm-scale passive inductors, the circuit has a notably reduced footprint (50 μm × 60 μm), facilitating its integration in a scalable quantum-classical architecture. The impedancemetry method has been applied at 4.2 K to the detection of quantum effects in the gate capacitance of on-chip nanometric CMOS transistors that are individually addressed via multiplexing.
In the strive for scalable quantum processors, significant effort is being devoted to the development of cryogenic classical hardware for the control and readout of a growing number of qubits. Here we report on a cryogenic circuit incorporating a CMOS-based active inductor enabling fast impedance measurements with a sensitivity of 10 aF and an input-referred noise of 3.7 aF/sqrt(Hz). This type of circuit is especially conceived for the readout of semiconductor spin qubits. As opposed to commonly used schemes based on dispersive rf reflectometry, which require mm-scale passive inductors, it allows for a markedly reduced footprint (50μm × 60μm), facilitating its integration in a scalable quantum-classical architecture. In addition, its active inductor results in a resonant circuit with tunable frequency and quality factor, enabling the optimization of readout sensitivity.
Compact and scalable quantum computer required physical qubits with low footprint and cryogenic electronics to be used in situ as standard control/readout system. The small spatial gap between the quantum chip and the cryogenic electronics limits the complexity of the wiring connections and the associated stray capacitance of the wires themselves, yielding a gain in terms of bandwidth and resolution. These improvements allow to design a fully-integrated CMOS readout based on current measurements with similar performances compared to the most common RF reflectometry-based readout technique. Here, we propose an acquisition system, operating at 4.2 K, which converts the spin dependent current coming from a single-electron transistor charge sensor into a digital output with a small power consumption (1 mW/qubit) and small occupation area (2). The system on chip consists of a low noise active integrator for the spin current, feeding a programmable threshold comparator to provide a digital output of the qubit state. It exhibits a resolution of tens of pA over an average input current of 1 nA with a time resolution of 1 μs.Compared to spin-qubit readout based on RF-reflectometry techniques, our solution does not require bulky off-chip compo-nents and to handle microwave signal and fast analog-to digital converters.
Solid-state quantum computers require classical electronics to control and readout individual qubits and to enable fast classical data processing [1-3]. Integrating both subsystems at deep cryogenic temperatures [4], where solid-state quantum processors operate best, may solve some major scaling challenges, such as system size and input/output (I/O) data management [5]. Spin qubits in silicon quantum dots (QDs) could be monolithically integrated with complementary metal-oxide-semiconductor (CMOS) electronics using very-large-scale integration (VLSI) and thus leveraging over wide manufacturing experience in the semiconductor industry [6]. However, experimental demonstrations of integration using industrial CMOS at mK temperatures are still in their infancy. Here we present a cryogenic integrated circuit (IC) fabricated using industrial CMOS technology that hosts three key ingredients of a silicon-based quantum processor: QD arrays (arranged here in a non-interacting 3x3 configuration), digital electronics to minimize control lines using row-column addressing and analog LC resonators for multiplexed readout, all operating at 50 mK. With the microwave resonators (6-8 GHz range), we show dispersive readout of the charge state of the QDs and perform combined time- and frequency-domain multiplexing, enabling scalable readout while reducing the overall chip footprint. This modular architecture probes the limits towards the realization of a large-scale silicon quantum computer integrating quantum and classical electronics using industrial CMOS technology.
A scalable spin-qubit quantum processor requires fast, high-fidelity readout circuits operating at cryogenic temperatures (CTs). This work analyzes the radio frequency (RF) reflectometry readout mechanism to establish the link between conductance modulation, single-electron transistor (SET) matching network design, reflected signal power, and receiver (RX) noise temperature. Based on this analysis, a cryogenic RX architecture employing a passive switched-capacitor front-end is proposed. The front-end performs RF amplification and downconversion using transistors as switches, avoiding active RF amplification and mitigating shot-noise limitations. The RX is implemented in 40-nm CMOS and operates from 100 MHz to 2.2 GHz. Measurements demonstrate a minimum noise temperature of approximately 15 K at 4.2 K. When integrated with a quantum device, the RX achieves a signal-to-noise ratio (SNR) of 9.8 dB for a 10-µs integration time and enables 99.9% charge-state readout fidelity without external cryogenic amplifiers. This work represents the first demonstration of such fidelity using a cryo-CMOS RX and constitutes an important step toward scalable integration of qubit readout electronics.
Thousands to millions of sensitive signals will need to be conveyed through all the temperature stages of a dilution fridge to operate future large-scale quantum processors made of many quantum bits. The exploding number of heat-conductive coaxial cables will overwhelm the fridge cooling capabilities, detrimental to the quantum core. Moving the control electronics down to cryogenic temperatures allows the use of already-available superconducting cables, alleviating heat conduction between low-temperature stages, and appears as a clear path towards scalability in the number of operating qubits.This Ph.D. work aimed to explore the use of the industrial CMOS 28nm Fully-Depleted Silicon-On-Insulator (FD-SOI) technology at cryogenic temperatures for quantum computing applications. Our first objective is to extend the sparse existing knowledge about the FD-SOI 28nm transistors at cryogenic temperatures for practical aspects of circuit design and later for developments of compact models.To speed-up the characterization of single devices with the inherent hour-long cooling cycles, we designed an integrated circuit multiplexing a thousand of transistors for different geometries and gate-stack flavors for low-frequency measurement of the current-voltage characteristics and pair-matching analysis from 300 down to 0.1K. We discuss and analyze the evolution trends with varying geometry at different temperatures for important quantities in circuit design, such as the transconductance, the conductance, and the transconductance over drain current ratio of individual transistors.Secondly, we explore the low-temperature co-integration and the full on-chip integration of semiconductor quantum devices with classical electronics aimed at specific measurements down to the millikelvin range.We first focus on the sub-nanoampere current measurement of quantum dot devices by designing and characterizing a low-power transimpedance amplifier (TIA). The high-gain amplifier is successfully applied to measure the current across single- and double quantum-dot devices, respectively wire-bonded a few mm away or on-chip integrated a few micrometers-away. To further leverage the integration into the same substrate, we connected GHz-range voltage-controlled oscillators to one of the gates of the double dot in an attempt to observe discrete charge pumping in a fully-integrated device.Lastly, we tackled the measurement of the gate capacitance of single quantum devices by proposing a new measurement scheme making use of the cryogenic electronics capabilities as an alternative to the well-known reflectometry. By integrating a voltage-controlled current excitation and a voltage-sensing amplifier in the 200 MHz range, both in close proximity to the quantum device connected to an LC tank, the read-out circuitry of a variation in the device capacitance becomes a purely lumped-element system with impedance measurement of the resonant circuit without any wave propagation like in reflectometry. This approach increases simplicity and compactness of the measurement set-up. We even replace the bulky passive inductor used in reflectometry by an active inductor made of transistors and capacitors, offering improved scalability with a 3-orders of magnitude lower area for the same inductance. The resulting circuit successfully measured aF-capacitance variations of nanometric transistors at 4.2K revealing oscillatory quantum effects in the gate capacitance as a function of the gate and back-gate voltages.At the end of this dissertation, a picture is given with the challenges laying ahead related to circuit architecture and design for the ultimate goal of entering into the era of large-scale quantum processing.
Quantum computing promises to revolutionize our lives, achieving unprecedented computational powers and unlocking new possibilities in drug discovery, chemical simulations and cryptography. The fundamental unit of computation of a quantum computer is the quantum bit (qubit). It can be implemented in a number of technologies, such as superconducting qubits, spin qubits, photonic systems, trapped ions and NV-centers. Solid-state superconducting qubits and spin qubits seem to be the most promising ones, as shown by the recent demonstration of quantum supremacy with a superconducting qubit processor. Such quantum processors, to operate in the quantum regime, require very low temperatures around 10 mK, and they are hence kept inside dilution fridges. The electronics required to read out and control such processors is typically realized by discrete components or bulky scientific instruments at room temperature wired into the dilution fridge. Such approach is only feasible until few (< 100) qubits are handled, but it is not scalable for million-qubit processors required for fault-tolerant operation. In this thesis, readout and control electronics is proposed to be integrated and operated directly at cryogenic temperatures, in close proximity with the qubits and potentially even co-integrated. CMOS technology is advocated for its scalability, compactness and low prototyping cost, to create a comprehensive cryo-CMOS class of fully-integrated transceivers to read out and control solid-state qubits. In particular, the thesis focuses on cryo-CMOS radio-frequency integrated circuits for the readout of silicon quantum computers, looking to integrate the whole readout system, from the quantum layer to the room temperature user interface. Cryogenic CMOS devices are explored first, to lay the foundations of integrated circuit design. The realization of quantum dots in standard CMOS technology is explored as a platform to realize solid-state qubit arrays, demonstrating functionality at 50 mK and good reproducibility. Moreover, the operation of integrated transistors at 50 mK and 4.2 K is explored to understand their basic cryogenic functionality, through characterization and modeling. Then also integrated passives, such as capacitors, inductors and transformers, are studied and modeled at cryogenic temperatures. Then, a fully-integrated readout platform spanning across all the blocks needed for dispersive readout is proposed. A fully-integrated matrix of quantum dots with radio-frequency gate-based readout capabilities is demonstrated along with time- and frequency-multiplexing. This quantum-classical circuit shows all the features for a scalable approach and is the core of the platform following it. A cryogenic CMOS circulator based on a new all-pass filter architecture is demonstrated, to be used as integrated replacement for current bulky counterparts; it allows power reduction, insertion loss and bandwidth enhancement with respect to state-of-the-art integrated circulators. The rest of the front-end is also explored with dedicated test multiplexers, a low noise-amplifier and an oscillator, that are finally merged in a single fully-integrated low-noise receiver with frequency synthesizer operating at 3.5 K for scalable multiplexed readout of silicon qubits. The platform presented in this thesis, across temperature boundaries, carries all the features required for future scalable silicon quantum computing platforms and could therefore form their core.