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Implementation and low speed test of ultra-fast interface circuits for Josephson-CMOS hybrid memories

K. Fujiwara, H Miyakawa, Nobuyuki Yoshikawa +3 more

Physica C SuperconductivityMay 28, 20031 citation

Input and output interfaces between RSFQ and semiconductor circuits

R. Koch, W. Jutzi

Physica C SuperconductivityNov 1, 19992 citations

RSFQ Baseband Digital Signal Processing

Anna Herr

Ultra fast switching speed of superconducting digital circuits enable realization of Digital Signal Processors with performance unattainable by any other technology. Based on rapid-single-flux technology (RSFQ) logic, these integrated circuits are capable of delivering high computation capacity up to 30 GOPS on a single processor and very short latency of 0.1ns. There are two main applications of such hardware for practical telecommunication systems: filters for superconducting ADCs operating with digital RF data and recursive filters at baseband. The later of these allows functions such as multiuser detection for 3G WCDMA, equalization and channel precoding for 4G OFDM MIMO, and general blind detection. The performance gain is an increase in the cell capacity, quality of service, and transmitted data rate. The current status of the development of the RSFQ baseband DSP is discussed. Major components with operating speed of 30GHz have been developed. Designs, test results, and future development of the complete systems including cryopackaging and CMOS interface are reviewed.Ultra fast switching speed of superconducting digital circuits enable realization of Digital Signal Processors with performance unattainable by any other technology. Based on rapid-single-flux technology (RSFQ) logic, these integrated circuits are capable of delivering high computation capacity up to 30 GOPS on a single processor and very short latency of 0.1ns. There are two main applications of such hardware for practical telecommunication systems: filters for superconducting ADCs operating with digital RF data and recursive filters at baseband. The later of these allows functions such as multiuser detection for 3G WCDMA, equalization and channel precoding for 4G OFDM MIMO, and general blind detection. The performance gain is an increase in the cell capacity, quality of service, and transmitted data rate. The current status of the development of the RSFQ baseband DSP is discussed. Major components with operating speed of 30GHz have been developed. Designs, test results, and future development of the complete systems including cryopackaging and CMOS interface are reviewed.

IEICE Transactions on ElectronicsMar 1, 20087 citations

초전도 디지털 RSFQ 논리회로와 실리콘 CMOS 회로와의 기술적 비교

조원, Gyu Moon

Mar 1, 20060 citations

Component development for a 16 Gb/s RSFQ-CMOS interface system

Nobuyuki Yoshikawa, Toshio Abe, Yuichi Kato +1 more

We have been developing an RSFQ-CMOS interface system. The system consists of three modules: a 1 to 32 bit DDST demultiplexer which converts a 16 Gb/s SFQ data input into a 32-channel 500 Mb/s output, asynchronous stacked-SQUID amplifiers which amplify an SFQ data input into a 5 mV voltage level output, and 77 K CMOS amplifiers which amplify a 5 mV voltage level input into a 5 V output at 500 MHz. We have implemented the asynchronous stacked-SQUID amplifier and the 77 K CMOS amplifier using the HYPRES 1 kA/cm/sup 2/ Nb process and the ROHM 0.6 /spl mu/m CMOS process, respectively. It was demonstrated that the 24-stage asynchronous stacked-SQUID amplifier amplifies an SFQ data input into a 2.0 mV voltage level at 600 MHz. The 77 K CMOS amplifier was shown to amplify a 5 mV voltage level input into 5 V at 500 MHz from the simulation, and a 175 mV voltage input into 3.5 V at 90 MHz from the experiment.We have been developing an RSFQ-CMOS interface system. The system consists of three modules: a 1 to 32 bit DDST demultiplexer which converts a 16 Gb/s SFQ data input into a 32-channel 500 Mb/s output, asynchronous stacked-SQUID amplifiers which amplify an SFQ data input into a 5 mV voltage level output, and 77 K CMOS amplifiers which amplify a 5 mV voltage level input into a 5 V output at 500 MHz. We have implemented the asynchronous stacked-SQUID amplifier and the 77 K CMOS amplifier using the HYPRES 1 kA/cm/sup 2/ Nb process and the ROHM 0.6 /spl mu/m CMOS process, respectively. It was demonstrated that the 24-stage asynchronous stacked-SQUID amplifier amplifies an SFQ data input into a 2.0 mV voltage level at 600 MHz. The 77 K CMOS amplifier was shown to amplify a 5 mV voltage level input into 5 V at 500 MHz from the simulation, and a 175 mV voltage input into 3.5 V at 90 MHz from the experiment.

IEEE Transactions on Applied SuperconductivityMar 1, 20019 citations

Engineering issues in high-frequency RSFQ circuits

T. Van Duzer, L Zheng, Xiangchao Meng +6 more

Physica C SuperconductivityAug 1, 200216 citations

Development and test of a fast RSFQ-CMOS interface

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