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IEEE International Conference on Quantum Computing and Engineering (QCE)

Square-Wave Defined Pulse Generator for High Fidelity Gate Operation of Superconducting Qubits

Ryosuke Matsuo, Kazuhisa Ogawa, Hidehisa Shiorni, Makoto Negoro, Ryutaro Ohira, Takefumi Miyoshi, Michihiro Shintani, Hiromitsu Awano, Takashi G. Sato, Jun Shiomi

Published Sep 15, 2024• 1 citation
Publisher

Abstract

Superconducting qubits are the promising candidate to realize large-scale quantum computing systems. Well-known quantum algorithms, such as Shor's algorithm, require at least$10^{5}$to$10^{6}$qubits to execute. Accordingly, classical systems for controlling superconducting qubits must also be scalable. One critical scalability challenge lies in the circuit cost of an RF pulse generator used to implement quantum gate operations. This poster proposes a cost-effective architecture for an RF pulse generator tailored to superconducting qubits. Most existing works use arbitrary waveform generators (AWGs) that require both a high-bandwidth memory (HBM) and a high-performance digital-analog converter (DAC) to achieve the highest gate fidelity with an optimized RF pulse waveform. The proposed pulse generator architecture significantly simplifies both the generator circuit and the waveform of the RF pulse to cost-aware square pulses. This architecture eliminates the requirement for power- and cost-intensive AWG, which is a major obstacle in realizing scalable quantum computers. Additionally, this poster demonstrates that our architecture can mitigate the error source associated with simplified RF pulses. Quantum dynamics simulation of transmon qubits, wherein the state of the system evolves with time, demonstrates that our pulse generator can achieve practically the same fidelity of gate operations for single and multiple qubits as ideal RF pulses while substantially reducing the sampling rate of DACs and the bandwidth of memories.

DOI
10.1109/qce60285.2024.10314

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•Jan 1, 2025•0 citations
Superconducting qubits are the promising candidate to realize large-scale quantum computing systems. Well-known quantum algorithms, such as Shor's algorithm, require at least10510^{5}105to10610^{6}106qubits to execute. Accordingly, classical systems for controlling superconducting qubits must also be scalable. One critical scalability challenge lies in the circuit cost of an RF pulse generator used to implement quantum gate operations. This poster proposes a cost-effective architecture for an RF pulse generator tailored to superconducting qubits. Most existing works use arbitrary waveform generators (AWGs) that require both a high-bandwidth memory (HBM) and a high-performance digital-analog converter (DAC) to achieve the highest gate fidelity with an optimized RF pulse waveform. The proposed pulse generator architecture significantly simplifies both the generator circuit and the waveform of the RF pulse to cost-aware square pulses. This architecture eliminates the requirement for power- and cost-intensive AWG, which is a major obstacle in realizing scalable quantum computers. Additionally, this poster demonstrates that our architecture can mitigate the error source associated with simplified RF pulses. Quantum dynamics simulation of transmon qubits, wherein the state of the system evolves with time, demonstrates that our pulse generator can achieve practically the same fidelity of gate operations for single and multiple qubits as ideal RF pulses while substantially reducing the sampling rate of DACs and the bandwidth of memories.
This paper proposes a cost-effective architecture for an RF pulse generator for superconducting qubits. Most existing works use arbitrary waveform generators (AWGs) that require both a large amount of high-bandwidth memories and high-performance analog circuits to achieve the highest gate fidelity with an optimized RF pulse waveform. The proposed pulse generator architecture significantly simplifies both the generator circuit and the waveform of the RF pulse to a cost-aware square pulses. This architecture eliminates the requirement for power- and cost-intensive AWG, a major obstacle in realizing scalable quantum computers. Additionally, this paper proposes a process to optimize pulse waveforms to maximize fidelity of gate operations for single and multiple qubits. Quantum dynamics simulation of transmon qubits, wherein the state of system evolves with time, demonstrates that our pulse generator can achieve practically the same gate fidelity as ideal RF pulses, while substantially reducing the performance requirements of memory and analog circuits.
Superconducting quantum processors are manufactured based on a semiconductor process, which makes qubit integration possible. At the same time, this kind of qubit exhibits high-performance fidelity and decoherence time and requires a programmable arbitrary waveform generator (AWG). This paper presents the implementation of an AWG with a sampling rate of two-gigabit samples per second as well as 16-bit vertical resolution digital-to-analog converters. The AWGs are designed for a scaled-up usage scenario by integrating them with separate microwave devices onto a single backplane. A special waveform sequence output controller is designed to realize seamless waveform switching and arbitrary waveform generation. The jitter of multiple AWG channels is around 10 ps, and the integral nonlinearity and differential nonlinearity are both about 2 least significant bits. This customizable AWG has been used in several superconducting quantum processors, and the result of multiple qubits’ measurement verifies that the AWG is qualified for controlling tens of superconducting qubits.
This paper reports the development of a low-latency arbitrary waveform generator (AWG), which is suitable for the control and measurement of superconducting quantum computers. It can generate qubit control signals and measurement signals in real time. Compared with commercial AWG, our AWG has less latency and higher analog bandwidth. Compressing latency can reduce system feedback time, and higher analog bandwidth improves the system's integration by mounting more qubits on the readout line. The AWG integrates four high-speed digital-to-analog converters (DACs), phase-locked loop (PLL) circuits, field-programmable gate arrays (FPGAs), and related circuits into a standard PXI 3U board. The waveform generator module, communication interface module, clock module, and configuration module are realized utilizing the FPGA. The FPGA-based hardware architecture enables AWG to be flexibly configured to meet the various needs of quantum experiments. The four-channel AWG has a 2-GSa/s sampling rate, a 14-bit resolution, and 500 MHz bandwidth. The jitter in the AWG output waveform is approximately 3 ps; the latency of the AWG (the time from the feedback trigger received until a feedback pulse is generated) is approximately 55 ns. These designs form the basis of realizing control system for large-scale quantum computing.
Control electronics for superconducting quantum processors have strict requirements for accurate command of the sensitive quantum states of their qubits. Hinging on the purity of ultra-phase-stable oscillators to upconvert very-low-noise baseband pulses, conventional control systems can become prohibitively complex and expensive when scaling to larger quantum devices, especially as high sampling rates become desirable for fine-grained pulse shaping. Few-gigahertz radio-frequency (RF) digital-to-analog converters (DACs) present a more economical avenue for high-fidelity control while simultaneously providing greater command over the spectrum of the synthesized signal. Modern RF DACs with extra-wide bandwidths are able to directly synthesize tones above their sampling rates, thereby keeping the system clock rate at a level compatible with modern digital logic systems while still being able to generate high-frequency pulses with arbitrary profiles. We have incorporated custom superconducting qubit control logic into off-the-shelf hardware capable of low-noise pulse synthesis up to 7.5 GHz using an RF DAC clocked at 5 GHz. Our approach enables highly linear and stable microwave synthesis over a wide bandwidth, giving rise to high-resolution control and a reduced number of required signal sources per qubit. We characterize the performance of the hardware using a five-transmon superconducting device and demonstrate consistently reduced two-qubit gate error (as low as 1.8%), which we show results from superior control chain linearity compared to traditional configurations. The exceptional flexibility and stability further establish a foundation for scalable quantum control beyond intermediate-scale devices.
Superconducting quantum computer is manufactured based on semiconductor process which makes qubits integration possible. At the same time, this kind of qubit exhibits high performance fidelity, de-coherence time, scalability and requires a programmable arbitrary waveform generator (AWG). This paper presents implementation of an AWG which composed of two gigabit samples per second (GSPS) sampling rate, 16 bit vertical resolution digital to analog converters (DACs). The AWG integrated with separate microwave devices onto a metal plate for the scale-up consideration. A special waveform sequence output controller is designed to realize seamless waveform switching and arbitrary waveform generator. The jitter in multiple AWG channels is around 10ps, Integral nonlinearity (INL) as well as differential nonlinearity (DNL) is about 2 LSB, and the qubit performance of the de-coherence time (T2*) achieved 33% promotion over that of a commercial 1 GSPS, 14 bit AWG.
Arbitrary Waveform Generators (AWGs) have widespread applications in telecommunications, quantum computing, and biomedical engineering, among others, due to their ability to generate a wide range of waveforms precisely and instantaneously. This work focuses on developing a scalable and energy-efficient AWG for qubit control. A simple methodology for bringing up a Radio-Frequency System-on-Chip (RFSoC) board and using it to generate various arbitrary waveforms has been discussed. A software-hardware codesign paradigm has been used in this work to dynamically control the output frequency, voltage and shape of the arbitrary waveforms. Similarly, the on-the-fly programmability of four Digital to Analog convertor (DAC) channels and four Analog to Digital Converter (ADC) channels have been tested. The voltage and frequency response of the DAC output has also been characterised to better understand the limitations of the RFSoC. The DAC-ADC loopback characterisation was also performed to prepare the RFSoC for qubit state readout measurements. Over the last few decades, the Direct Digital Synthesiser (DDS) has been a popular choice for generating specific waveforms, such as sinusoidal and ramp waveforms, due to its low cost, simple design, and high precision. Several prior-art works were surveyed, and the trade-offs and strengths of each architecture were summarised. A benchmarking table is prepared based on the Power, Performance and Area (PPA) analysis to make design selection easier for DDS designers. Two Figure of Merit definitions and scaling equations have also been used to normalise the specifications to a target process node (28 nm CMOS), to provide a more accurate comparison among state-of-the-art DDS designs on Application Specific Integrated Circuits (ASICs), and to set expectations for future architectural advancements in DDS design. Finally, a viable DDS-based AWG architecture for ASIC implementation has also been proposed based on the benchmarking.