Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Quantum 2.0 Conference and Exhibition

FPGA-based Time-to-digital Converter for Quantum Key Distribution with continuous calibration

Matías Rubén Bolaños, Daniele Vogrig, Paolo Villoresi, Giuseppe Vallone, Andrea Stanco

Published Jan 1, 2024• 0 citations
Publisher

Abstract

In this work, we introduce a scalable, multichannel FPGA-based time-to-digital converter design for quantum key distribution. Our approach includes a non-disruptive calibration scheme, enabling continuous data acquisition and enhancing system performance.
DOI
10.1364/quantum.2024.qw3a.38

Related papers

A Time-to-Digital Converter With Steady Calibration Through Single-Photon Detection

Matías Rubén Bolaños, Daniele Vogrig, Paolo Villoresi +2 more

Time-to-Digital Converters (TDCs) are a crucial tool in a wide array of fields, in particular for quantum communication, where time taggers performance can severely affect the quality of the entire application. Nowadays, FPGA-based TDCs present a viable alternative to ASIC ones, once the non-linear behavior due to the intrinsic nature of the device is properly mitigated. To compensate for said nonlinearities, a calibration procedure is required, which should be maintained throughout its runtime. Here we present the design and the demonstration of a TDC that is FPGA-based showing a residual FWHM jitter of 27 ps, that is scalable for multichannel operation. The target application in Quantum Key Distribution (QKD) is discussed with a calibration method based on the exploitation of single-photon detection that does not require stopping the data acquisition or using any estimation methods, thus increasing accuracy and removing data loss. The calibration was tested in a relevant environment, investigating the behavior of the device between 5 °C and 80 °C. Moreover, our design is capable of continuously streaming up to 12 Mevents/s for up to ~1 week without the TDC overflowing making it ready for a real-life scenario deployment.

arXiv:2406.01293•IEEE Transactions on Instrumentation and Measurement•Jan 1, 2025•7 citations

An FPGA-Based TDC for Free Space Quantum Key Distribution

Qi Shen, Sheng‐Kai Liao, Shubin Liu +4 more

Quantum key distribution (QKD) is the most matured application of quantum communication. The time synchronization and system timing jitter are essential to a practical QKD experiment, which can directly influence the quantum bit error rate (QBER) and the final key rate. High precision time-to-digital converters (TDCs) can effectively reduce the system timing jitter, resulting in lower QBER and higher key rate. Here, we introduce a TDC based on a field programmable gate array (FPGA). Its high resolution (LSB) of 50 ps with precision (RMS) less than 50 ps, low dead time and large dynamic range can well meet the requirement of the QKD experiment. A free space QKD system setup using the FPGA-based TDC has been assembled. The timing precision of the synchronous light and the system timing jitter were determined. The results demonstrate that the FPGA-based TDC could be successfully applied in the QKD experiment.

IEEE Transactions on Nuclear Science•Oct 1, 2013•25 citations

A Security-Aware Nonlinearity Study of FPGA-Based Time-to-Digital Converters for Quantum Key Distribution Systems

Kun Qin, Carsten Trinitis

Intrinsic nonlinearity in FPGA-based time-to-digital converters (TDCs) is often treated as a calibration issue and evaluated mainly through post-correction metrics. In quantum key distribution (QKD), however, raw delay-line nonuniformity can affect coincidence timing and thereby influence accidental-coincidence rate and Quantum Bit Error Rate (QBER). This paper analyzes how measured FPGA-TDC nonlinearity propagates to QKD timing metrics using a conservative system-level model that combines random timing uncertainty and deterministic nonlinearity. We also propose fabric-level mitigation strategies based on LUT-assisted delay shaping and placement constraints to reduce severe bin-width irregularities without statistical calibrations. The method is evaluated by reproducing two open-source TDCs implemented on a low-cost Zynq-7000 FPGA. We observe reductions of 14\%-21\% in integral nonlinearity (INL) compared with the non-optimized design, leading to a reduced QBER contribution and an improvement by 3.7\%-14.2\% in the estimated secret fraction. These results suggest that raw FPGA-TDC nonlinearity deserves explicit consideration in timing-sensitive QKD implementations.

quant-pharXiv:2604.00229•Apr 2, 2026•0 citations

Time interval analyzer with FPGA-based TDC for free space quantum key distribution: Principle and validation with prototype setup

Qi Shen, Sheng‐Kai Liao, Shubin Liu +4 more

Quantum key distribution (QKD) is the most matured application of quantum communication. The time synchronization and system timing jitter are essential to a practical QKD experiment, which can directly influence the quantum bit error rate (QBER) and the final key rate. High precision time-to-digital convertor (TDC) can effectively reduce the system timing jitter, resulting in lower QBER and higher key rate. Here, we introduce a TDC based on a field-programmable gate array (FPGA). Its high resolution of 50 ps, low dead time and large dynamic range can well meet the requirement of the QKD experiment. A free space QKD system setup using the FPGA-based TDC has been built up. The timing precision of the synchronous light and the system timing jitter were tested. The results demonstrate that the FPGA-based TDC could be successfully applied in the QKD experiment.

IEEE-NPSS Real-Time Conference•Jun 1, 2012•3 citations

Ultrafast quantum key distribution using fully parallelized quantum channels

Robin Terhaar, Jasper Rödiger, Matthias Häußler +16 more

The field of quantum information processing offers secure communication protected by the laws of quantum mechanics and is on the verge of finding wider application for the information transfer of sensitive data. To improve cost-efficiency, extensive research is being carried out on the various components required for high data throughput using quantum key distribution (QKD). Aiming for an application-oriented solution, we report the realization of a multichannel QKD system for plug-and-play high-bandwidth secure communication at telecom wavelengths. We designed a rack-sized multichannel superconducting nanowire single photon detector (SNSPD) system, as well as a highly parallelized time-correlated single photon counting (TCSPC) unit. Our system is linked to an FPGA-controlled QKD evaluation setup for continuous operation, allowing us to achieve high secret key rates using a coherent-one-way protocol.

arXiv:2207.07345•Optics Express•Dec 9, 2022•27 citations

Delay Time Characterization on FPGA: A Low Nonlinearity, Picosecond Resolution Time-to-Digital Converter on 16-nm FPGA using Bin Sequence Calibration

Sunwoo Park, Byungkwon Park, Eunsung Kim +3 more

We present a Time-to-Digital Converter (TDC) implemented on a 16 nm Xilinx UltraScale Plus FPGA that achieves a resolution of 1.15 ps, RMS precision of 3.38 ps, a differential nonlinearity (DNL) of [-0.43, 0.24] LSB, and an integral nonlinearity (INL) of [-2.67, 0.15] LSB. This work introduces two novel hardware-independent post-processing techniques - Partial Order Reconstruction (POR) and Iterative Time-bin Interleaving (ITI) - that significantly enhance the performance of FPGA-based TDCs. POR addresses the missing code problem by inferring the partial order of each time bin through code density test data and directed acyclic graph (DAG) analysis, enabling near-complete recovery of usable bins. ITI further improves fine time resolution by merging multiple calibrated tapped delay lines (TDLs) into a single unified delay chain, achieving scalable resolution without resorting to averaging. Compared to state-of-the-art FPGA-based TDC architectures, the proposed methods deliver competitive or superior performance with reduced hardware overhead. These techniques are broadly applicable to high-resolution time measurement and precise delay calibration in programmable logic platforms.

cs.ARCross-listedarXiv:2511.05583•Nov 6, 2025
Time-to-Digital Converters (TDCs) are a crucial tool in a wide array of fields, in particular for quantum communication, where time taggers performance can severely affect the quality of the entire application. Nowadays, FPGA-based TDCs present a viable alternative to ASIC ones, once the non-linear behavior due to the intrinsic nature of the device is properly mitigated. To compensate for said nonlinearities, a calibration procedure is required, which should be maintained throughout its runtime. Here we present the design and the demonstration of a TDC that is FPGA-based showing a residual FWHM jitter of 27 ps, that is scalable for multichannel operation. The target application in Quantum Key Distribution (QKD) is discussed with a calibration method based on the exploitation of single-photon detection that does not require stopping the data acquisition or using any estimation methods, thus increasing accuracy and removing data loss. The calibration was tested in a relevant environment, investigating the behavior of the device between 5 °C and 80 °C. Moreover, our design is capable of continuously streaming up to 12 Mevents/s for up to ~1 week without the TDC overflowing making it ready for a real-life scenario deployment.
Quantum key distribution (QKD) is the most matured application of quantum communication. The time synchronization and system timing jitter are essential to a practical QKD experiment, which can directly influence the quantum bit error rate (QBER) and the final key rate. High precision time-to-digital converters (TDCs) can effectively reduce the system timing jitter, resulting in lower QBER and higher key rate. Here, we introduce a TDC based on a field programmable gate array (FPGA). Its high resolution (LSB) of 50 ps with precision (RMS) less than 50 ps, low dead time and large dynamic range can well meet the requirement of the QKD experiment. A free space QKD system setup using the FPGA-based TDC has been assembled. The timing precision of the synchronous light and the system timing jitter were determined. The results demonstrate that the FPGA-based TDC could be successfully applied in the QKD experiment.
Intrinsic nonlinearity in FPGA-based time-to-digital converters (TDCs) is often treated as a calibration issue and evaluated mainly through post-correction metrics. In quantum key distribution (QKD), however, raw delay-line nonuniformity can affect coincidence timing and thereby influence accidental-coincidence rate and Quantum Bit Error Rate (QBER). This paper analyzes how measured FPGA-TDC nonlinearity propagates to QKD timing metrics using a conservative system-level model that combines random timing uncertainty and deterministic nonlinearity. We also propose fabric-level mitigation strategies based on LUT-assisted delay shaping and placement constraints to reduce severe bin-width irregularities without statistical calibrations. The method is evaluated by reproducing two open-source TDCs implemented on a low-cost Zynq-7000 FPGA. We observe reductions of 14\%-21\% in integral nonlinearity (INL) compared with the non-optimized design, leading to a reduced QBER contribution and an improvement by 3.7\%-14.2\% in the estimated secret fraction. These results suggest that raw FPGA-TDC nonlinearity deserves explicit consideration in timing-sensitive QKD implementations.
Quantum key distribution (QKD) is the most matured application of quantum communication. The time synchronization and system timing jitter are essential to a practical QKD experiment, which can directly influence the quantum bit error rate (QBER) and the final key rate. High precision time-to-digital convertor (TDC) can effectively reduce the system timing jitter, resulting in lower QBER and higher key rate. Here, we introduce a TDC based on a field-programmable gate array (FPGA). Its high resolution of 50 ps, low dead time and large dynamic range can well meet the requirement of the QKD experiment. A free space QKD system setup using the FPGA-based TDC has been built up. The timing precision of the synchronous light and the system timing jitter were tested. The results demonstrate that the FPGA-based TDC could be successfully applied in the QKD experiment.
The field of quantum information processing offers secure communication protected by the laws of quantum mechanics and is on the verge of finding wider application for the information transfer of sensitive data. To improve cost-efficiency, extensive research is being carried out on the various components required for high data throughput using quantum key distribution (QKD). Aiming for an application-oriented solution, we report the realization of a multichannel QKD system for plug-and-play high-bandwidth secure communication at telecom wavelengths. We designed a rack-sized multichannel superconducting nanowire single photon detector (SNSPD) system, as well as a highly parallelized time-correlated single photon counting (TCSPC) unit. Our system is linked to an FPGA-controlled QKD evaluation setup for continuous operation, allowing us to achieve high secret key rates using a coherent-one-way protocol.
We present a Time-to-Digital Converter (TDC) implemented on a 16 nm Xilinx UltraScale Plus FPGA that achieves a resolution of 1.15 ps, RMS precision of 3.38 ps, a differential nonlinearity (DNL) of [-0.43, 0.24] LSB, and an integral nonlinearity (INL) of [-2.67, 0.15] LSB. This work introduces two novel hardware-independent post-processing techniques - Partial Order Reconstruction (POR) and Iterative Time-bin Interleaving (ITI) - that significantly enhance the performance of FPGA-based TDCs. POR addresses the missing code problem by inferring the partial order of each time bin through code density test data and directed acyclic graph (DAG) analysis, enabling near-complete recovery of usable bins. ITI further improves fine time resolution by merging multiple calibrated tapped delay lines (TDLs) into a single unified delay chain, achieving scalable resolution without resorting to averaging. Compared to state-of-the-art FPGA-based TDC architectures, the proposed methods deliver competitive or superior performance with reduced hardware overhead. These techniques are broadly applicable to high-resolution time measurement and precise delay calibration in programmable logic platforms.