This work reviews methods for optimizing quantum circuit depth, encompassing theoretical techniques, algorithmic innovations, and practical applications. Recent advancements demonstrate substantial improvements in circuit depth optimization, yet the issue of scalability remains unresolved. Key research contributions, such as the advanced exact synthesis of Clifford+T circuits, have shown promising results in reducing the number of T-gates, thus enhancing computational efficiency. However, the practical implementation of these methods in real-world noisy environments has yet to be fully evaluated. Further studies have developed automated optimization techniques for large quantum circuits with continuous parameters, significantly minimizing gate counts while maintaining structural integrity. Despite these advancements, challenges persist in assessing the performance of these optimized circuits on actual quantum hardware and integrating them into various quantum algorithms. The qubit routing problem also presents significant hurdles, particularly in systems with limited communication, necessitating effective methodologies to optimize qubit placement and movement. A comprehensive full-stack approach, incorporating hardware, software, and compiler optimizations, has provided valuable insights into architectural comparisons and design strategies. This approach highlights the importance of noise-aware compilation and the need for microarchitecture-specific optimizations to improve program success rates on current quantum devices. This paper underscores the need for scalable, hardware-agnostic optimization methods and extensive experimental validation. Integrating graph neural networks for quantum circuit optimization presents a promising future research direction. The analysis concludes that while significant progress has been made, unresolved issues such as computational complexity, limited experimental validation, and the diversity of quantum algorithms necessitate ongoing research to fully realize the potential of quantum computing. In conclusion, optimizing the depth of quantum circuits is a multifaceted problem requiring continuous research and development. The integration of theoretical advancements with practical implementations is crucial for overcoming current limitations and unlocking the full potential of quantum computing. Continued efforts in this area will be vital for achieving scalable and efficient quantum computations
This work reviews methods for optimizing quantum circuit depth, encompassing theoretical techniques, algorithmic innovations, and practical applications. Recent advancements demonstrate substantial improvements in circuit depth optimization, yet the issue of scalability remains unresolved. Key research contributions, such as the advanced exact synthesis of Clifford+T circuits, have shown promising results in reducing the number of T-gates, thus enhancing computational efficiency. However, the practical implementation of these methods in real-world noisy environments has yet to be fully evaluated. Further studies have developed automated optimization techniques for large quantum circuits with continuous parameters, significantly minimizing gate counts while maintaining structural integrity. Despite these advancements, challenges persist in assessing the performance of these optimized circuits on actual quantum hardware and integrating them into various quantum algorithms. The qubit routing problem also presents significant hurdles, particularly in systems with limited communication, necessitating effective methodologies to optimize qubit placement and movement. A comprehensive full-stack approach, incorporating hardware, software, and compiler optimizations, has provided valuable insights into architectural comparisons and design strategies. This approach highlights the importance of noise-aware compilation and the need for microarchitecture-specific optimizations to improve program success rates on current quantum devices. This paper underscores the need for scalable, hardware-agnostic optimization methods and extensive experimental validation. Integrating graph neural networks for quantum circuit optimization presents a promising future research direction. The analysis concludes that while significant progress has been made, unresolved issues such as computational complexity, limited experimental validation, and the diversity of quantum algorithms necessitate ongoing research to fully realize the potential of quantum computing. In conclusion, optimizing the depth of quantum circuits is a multifaceted problem requiring continuous research and development. The integration of theoretical advancements with practical implementations is crucial for overcoming current limitations and unlocking the full potential of quantum computing. Continued efforts in this area will be vital for achieving scalable and efficient quantum computations
Abstract Quantum convolutional neural networks (QCNNs) are gaining increasing attention as a new class of models in quantum machine learning, especially for image classification and other computer vision tasks. Recent advances include the development of hybrid classical quantum models, novel quantum coding schemes, and innovative circuit architectures that enable efficient processing of high-dimensional visual data under the constraints of Noisy Intermediate-Scale Quantum (NISQ) devices. Despite the progress in QCNN design, practical deployment of these models is hampered by the complexity of quantum circuit implementation. Circuit depth, gate count, qubit connectivity, and hardware noise pose significant challenges to scalability and performance. As a result, quantum circuit optimization has become a critical area of research aimed at improving the efficiency of QCNNs, reducing quantum resource requirements, and improving classification accuracy. Among various approaches, heuristic and metaheuristic optimization methods such as genetic algorithms and evolutionary strategies have shown notable promise in addressing the high-dimensional and non-convex nature of the optimization space. This study presents a systematic literature review of 40 key research papers published between 2014 and 2025, 1 selected through strict inclusion and quality assessment criteria. The review covers key aspects of QCNN development, including architectures, coding strategies, and application areas, followed by an in-depth analysis of optimization method-ologies, objectives, and evaluation metrics. The results reveal emerging trends in hybrid quantum-classical integration, the widespread use of metaheuristic algorithms for circuit tuning, and the importance of multi-objective optimization frameworks tailored to the constraints of quantum computing. This review highlights critical research gaps and outlines future directions for advancing QCNN models and their practical implementation on quantum devices in the near future.
In recent decades, quantum computing has witnessed remarkable progress, achieved through various advancements across the technology stack, such as quantum error-correcting codes and quantum algorithms. It is noteworthy that several promising algorithms incorporate quantum arithmetic circuits as fundamental building blocks. However, the inherent properties of quantum circuits challenge the efficiency of quantum arithmetic circuits, prompting creative solutions. While several quantum arithmetic circuits have been proposed, there is still a substantial gap in quantum arithmetic circuits optimization. For example, methods for integrating classical techniques such as high radix strategy into quantum designs still remain underexplored, highlighting a significant space for further advancement. This thesis aims to improve the performance of quantum arithmetic designs by integrating classical arithmetic circuit design techniques. Specifically, this thesis contains the following research: (1) The utilization of classical higher radix strategy to enhance quantum addition, reducing overall cost by lowering T-depth and T-count. The proposed design outperforms existing quantum carry-lookahead adders. (2) The application of Ling structure, achieving a reduced Toffoli-depth of 4log(n/2). (3) The exploration of the Kogge-Stone architecture, resulting in the lowest Toffoli-depth of log(n) for quantum adders. (4) The development of an efficient modular addition framework using carry-save architecture, demonstrating a 33.3% improvement in Toffoli depth compared to existing designs. (5) The design of an optimized quantum non-restoring divider framework. (6) A comprehensive overview of current advancements in quantum arithmetic designs, offering insights into potential research directions. These proposed designs are mapped to real-world quantum hardware architectures, including Noisy Intermediate-Scale Quantum systems, to validate their functionality and evaluate efficiency. Their applications in quantum machine learning and cryptography further underscore the broader impact of these improvements. Overall, this thesis makes significant advancements in reducing quantum circuit depth and improving resource efficiency, contributing to the development of scalable and efficient large-scale quantum circuits. By adapting classical design strategies to quantum circuits, it not only enhances various quantum circuit designs but also fosters further exploration at the intersection of classical and quantum computing.
Quantum computing, a paradigm shift with the potential to revolutionize fields ranging from cryptography to optimization, is rapidly evolving. This survey delves into the key quantum computing architectures—gate-based and quantum annealing—and their profound impact on circuit design and optimization. Gate-based systems, such as those utilizing superconducting qubits and trapped ions, offer versatile platforms capable of executing a broad array of quantum algorithms. However, they present unique challenges for circuit designers, including noise sensitivity, scalability, and the need for complex error correction circuits. Quantum annealing, exemplified by D-Wave systems, offers a more specialized approach to solving optimization problems, requiring distinct circuit design considerations focused on energy efficiency and coherence preservation.This paper reviews the foundational research on these architectures, compares their respective design challenges, and examines the optimization techniques that have emerged in response to these challenges. Gate count reduction, error correction, and hybrid quantum-classical methods are highlighted as key approaches for improving circuit efficiency and scalability in quantum systems. Furthermore, this survey emphasizes the importance of interdisciplinary collaboration between quantum physicists, electrical engineers, and computer scientists to address the complex challenges associated with quantum circuit design. By combining expertise from these fields, researchers can develop innovative solutions that bridge the gap between theoretical concepts and practical hardware implementations. Ultimately, this survey underscores the need for continued innovation at the intersection of quantum computing and electrical engineering, as researchers strive to overcome current limitations and develop practical, large-scale quantum systems that can harness the full potential of this revolutionary technology.
Quantum convolutional neural networks (QCNNs) are emerging as promising models in quantum machine learning, particularly for image classification and computer vision tasks. Recent developments include hybrid classical–quantum architectures, advanced quantum encoding methods, and novel circuit designs that improve data processing on Noisy Intermediate-Scale Quantum (NISQ) devices. However, practical implementation remains challenging due to circuit complexity, gate count, qubit connectivity, and hardware noise, which limit scalability and performance. Consequently, quantum circuit optimization has become essential for reducing resource requirements and improving classification accuracy. This study presents a systematic literature review of 40 research papers published between 2014 and 2025. The review covers QCNNs together with closely related quantum neural network (QNN) models and quantum circuit optimization studies, since circuit-optimization techniques are frequently developed for QNNs more broadly rather than for QCNN architectures in isolation. Within this scope, it examines network architectures, encoding strategies, application domains, and optimization techniques, with particular attention to heuristic and metaheuristic approaches such as genetic algorithms and evolutionary strategies. The findings highlight growing trends in hybrid quantum–classical integration, the widespread adoption of metaheuristic optimization, and the importance of multi-objective frameworks adapted to quantum hardware constraints. Finally, the review identifies key research gaps and future directions for practical QCNN deployment on near-term quantum devices.
Quantum computing, leveraging the principles of superposition and entanglement, holds the potential to revolutionize computational problem-solving across a wide array of fields, from cryptography to complex system simulations. However, unlocking the full power of quantum computing requires the development of advanced quantum compilation techniques that can efficiently map high-level algorithms onto physical quantum hardware. This paper delves into state-of-the-art optimization strategies within quantum compilers, with a particular focus on methods such as Relaxed Peephole Optimization (RPO), gate reordering techniques for the Quantum Approximate Optimization Algorithm (QAOA), and reinforcement learning (RL)-driven frameworks. It also explores innovative approaches like distributed quantum compilation, parity quantum optimization, and the Paulihedral framework, all designed to minimize gate counts, reduce circuit depth, and optimize overall resource utilization. A key contribution of this work is the introduction of error mitigation techniques that enhance the fidelity and scalability of quantum circuits, particularly on noisy intermediate-scale quantum (NISQ) devices. Through comprehensive empirical evaluations across a variety of quantum algorithms, the paper demonstrates significant improvements in critical performance metrics such as circuit depth, gate count, and execution efficiency, providing a promising direction for optimizing quantum circuit design tailored to diverse quantum hardware platforms.
The rapid advancement of Noisy Intermediate-Scale Quantum (NISQ) devices has driven the need for efficient design automation tools that can translate complex engineering models into executable quantum circuits. This study explores the development of automated quantum circuit design frameworks focused on gate optimization and noise-aware compilation, enabling practical quantum computation for engineering applications such as optimization, simulation, and control systems. Traditional circuit design methods often fail to account for hardware constraints, decoherence, and gate infidelity, which significantly affect computational accuracy on NISQ devices. To address these challenges, this research introduces a hybrid automation approach combining quantum transpilation, variational circuit pruning, and error-aware synthesis algorithms to enhance circuit reliability and scalability. The framework integrates quantum-classical co-design principles to optimize both logical and physical circuit layers, leveraging hardware-specific calibration data to adapt compilation strategies dynamically. Through simulations and benchmark analysis, the proposed system demonstrates significant improvements in quantum resource utilization, error mitigation, and gate depth reduction compared to conventional compilation methods. This work underscores the growing importance of design automation in quantum engineering, where algorithmic efficiency must be harmonized with physical constraints to realize functional and scalable quantum workflows. By establishing a methodology for gate-level optimization and noise-adaptive design, the study contributes to bridging the gap between theoretical quantum algorithms and real-world engineering implementations within the NISQ computing era.