In this work, we present a Python framework designed to demonstrate various error types within quantum circuits through the utilization of probabilistic data obtained from quantum computers. The framework serves as a valuable tool for monitoring and mitigating errors across all stages of quantum circuits involving multiple qubits and gates. Leveraging the Harrow-Hassidim-Lloyd (HHL) quantum circuit, we conduct an analysis of errors on an IBM quantum computer and subsequently optimize the circuit. The paper introduces an automated methodology for computing single bit-flip errors and propagation errors, and gate errors offering insights into opportunities for mitigating errors in the context of the HHL quantum circuit.
In this work, we present a Python framework designed to demonstrate various error types within quantum circuits through the utilization of probabilistic data obtained from quantum computers. The framework serves as a valuable tool for monitoring and mitigating errors across all stages of quantum circuits involving multiple qubits and gates. Leveraging the Harrow-Hassidim-Lloyd (HHL) quantum circuit, we conduct an analysis of errors on an IBM quantum computer and subsequently optimize the circuit. The paper introduces an automated methodology for computing single bit-flip errors and propagation errors, and gate errors offering insights into opportunities for mitigating errors in the context of the HHL quantum circuit.
In this work, we present an automatic Python framework designed to perform heuristic error analysis of gate-based model algorithms running on a given quantum computer, to identify the source, the nature, and the bottleneck of errors. The information will allow quantum hardware-algorithm co-optimization. This is particularly useful for novel algorithms and hardware. By analyzing the relative contribution of the gate error, propagation error, bit-flip error, and measurement error at each node, one can then use the information to optimize the circuit in terms of the choice of gates and physical qubits. Since it is a model based on the probability of a state being measured, it cannot capture the crossterms and interference. However, it still can be used to deduce the node/stage that has a big error due to failure in interference. In this paper, the Harrow-Hassidim-Lloyd (HHL) quantum algorithm running on the IBM superconducting qubit platform is used as a demonstration of the framework. The bottleneck of the error in the HHL circuit is identified. It should also be noted that this framework can only be used for small problems because simulation is required on a classical computer.
Due to very high projected error rates, large scale quantum computers will require substantial fault tolerance just to maintain a minimum level of reliability. We present tools to better analyze the performance of large, fault tolerant quantum computer designs. We find that current uses of quantum error correction are overly conservative in mitigating the impact of gate errors and negligent of other error sources in quantum data communication and memory.
We have developed circuit layout heuristics to generate detailed designs in trapped ion quantum computing technology. From these designs, we can extract much more accurate error models for a given application, including all gate, movement and idle errors on qubits. Using these extracted models, our flexible error simulation environment determines the overall failure probability of the design. Included in this simulation environment is a bit-parallel Monte Carlo technique that is 10 times faster than previous fault propagation simulations. This allows us to evaluate the reliability of designs that are an order of magnitude larger, in the same amount of time.
Using this analysis framework to verify reliability, we have developed a linear programming-based optimization for error correction which decreases overall circuit resources by an order of magnitude. In some cases, our optimization actually improves overall system reliability by removing error correction. We combine this optimization with judicious quantum error correcting code selection to provide efficient designs for large quantum arithmetic kernels used in Shor's factorization algorithm. We show our optimized designs perform 2x to 100x better than previous works in terms of probabilistic area-delay product. Additionally, the area of our layout of a 1024-bit factoring using Shor's algorithm is 64cm2, a substantial improvement compared to the 0.9m2 state-of-the-art design from prior work. A design size reduction by this amount will make fabricating such an application feasible much sooner.
The rapid advancement of Noisy Intermediate-Scale Quantum (NISQ) devices has driven the need for efficient design automation tools that can translate complex engineering models into executable quantum circuits. This study explores the development of automated quantum circuit design frameworks focused on gate optimization and noise-aware compilation, enabling practical quantum computation for engineering applications such as optimization, simulation, and control systems. Traditional circuit design methods often fail to account for hardware constraints, decoherence, and gate infidelity, which significantly affect computational accuracy on NISQ devices. To address these challenges, this research introduces a hybrid automation approach combining quantum transpilation, variational circuit pruning, and error-aware synthesis algorithms to enhance circuit reliability and scalability. The framework integrates quantum-classical co-design principles to optimize both logical and physical circuit layers, leveraging hardware-specific calibration data to adapt compilation strategies dynamically. Through simulations and benchmark analysis, the proposed system demonstrates significant improvements in quantum resource utilization, error mitigation, and gate depth reduction compared to conventional compilation methods. This work underscores the growing importance of design automation in quantum engineering, where algorithmic efficiency must be harmonized with physical constraints to realize functional and scalable quantum workflows. By establishing a methodology for gate-level optimization and noise-adaptive design, the study contributes to bridging the gap between theoretical quantum algorithms and real-world engineering implementations within the NISQ computing era.
Current quantum computers suffer from a level of noise that prohibits extracting useful results directly from longer computations. The figure of merit in many near-term quantum algorithms is an expectation value measured at the end of the computation, which experiences a bias in the presence of hardware noise. A systematic way to remove such bias is probabilistic error cancellation (PEC). PEC requires a full characterization of the noise and introduces a sampling overhead that increases exponentially with circuit depth, prohibiting high-depth circuits at realistic noise levels. Probabilistic error reduction (PER) is a related quantum error mitigation method that systematically reduces the sampling overhead at the cost of reintroducing bias. In combination with zero-noise extrapolation, PER can yield expectation values with an accuracy comparable to PEC. Noise reduction through PER is broadly applicable to near-term algorithms, and the automated implementation of PER is thus desirable for facilitating its widespread use. To this end, we present an automated quantum error mitigation software framework that includes noise tomography and application of PER to user-specified circuits. We provide a multi-platform Python package that implements a recently developed Pauli noise tomography (PNT) technique for learning a sparse Pauli noise model and exploits a Pauli noise scaling method to carry out PER. We also provide software tools that leverage a previously developed toolchain, employing PyGSTi for gate set tomography and providing a functionality to use the software Mitiq for PER and zero-noise extrapolation to obtain error-mitigated expectation values on a user-defined circuit.
Quantum error correction (QEC) is vital for protecting quantum information against errors induced by quantum noise and decoherence, enabling fault-tolerant quantum computation. Here, we construct a SPICE-based classical emulator framework to simulate gate-based quantum error correction circuits, specifically designed to correct both bitflip and phase flip errors. In our framework, a collection of LC-oscillators emulates the process behavior quantum gates. Each quantum state is perfectly described by the phase and amplitude of each oscillator. Our framework is scalable to any quantum error correction system with any arbitrary number of qubits since each gate process is perfectly achieved. Here, we have successfully conducted simulations for an individual bit-flip correction circuit and Shor’s nine-bit error correcting quantum circuit, demonstrating the capability of our framework to effectively address and repair random bit-flip and phase flip errors in gate-based quantum computing circuits.
Near-term quantum computers have been built as intermediate-scale quantum devices and are fragile against quantum noise effects, namely, NISQ devices. Traditional quantum-error-correcting codes are not implemented on such devices and to perform quantum computation in good accuracy with these machines we need to develop alternative approaches for mitigating quantum computational errors. In this work, we propose quantum error mitigation (QEM) scheme for quantum computational errors which occur due to couplings with environments during gate operations, i.e., decoherence. To establish our QEM scheme, first we estimate the quantum noise effects on single-qubit states and represent them as groups of quantum circuits, namely, quantum-noise-effect circuit groups. Then our QEM scheme is conducted by subtracting expectation values generated by the quantum-noise-effect circuit groups from those obtained by the quantum circuits for the quantum algorithms under consideration. As a result, the quantum noise effects are reduced, and we obtain approximately the ideal expectation values via the quantum-noise-effect circuit groups and the numbers of elementary quantum circuits composing them scale polynomial with respect to the products of the depths of quantum algorithms and the numbers of register bits. To numerically demonstrate the validity of our QEM scheme, we run noisy quantum simulations of qubits under amplitude damping effects for four types of quantum algorithms. Furthermore, we implement our QEM scheme on IBM Q Experience processors and examine its efficacy. Consequently, the validity of our scheme is verified via both the quantum simulations and the quantum computations on the real quantum devices. Our QEM scheme is solely composed of quantum-computational operations (quantum gates and measurements), and thus, it can be conducted by any type of quantum device. In addition, it can be applied to error mitigation for many other types of quantum noise effects as well as noisy quantum computing of long-depth quantum algorithms.