IEEE Electronic Components and Technology Conference (ECTC)
Integration of planarized Nb-based vias to form a multi-level superconducting back-end-of-line
Candice Thomas, Edouard Deschaseaux, Rémi Vélard, Giovanni Romano, Jean-Philippe Michel, Norman Vivien, Richard Souil, Cassandre Beluffi, Simon Guignard, Catherine Pellissier, Jean Charbonnier
Scaling of solid-state quantum bits requires more and more complex connectivity schemes within two- or three-dimensional architectures. In that context, superconducting interconnects appear essential to tackle the associated challenges of compactness, thermal management and signal dispersion. We report on the fabrication of a two-level superconducting backend-of-line (BEOL) using 200 mm Si wafer technologies. This BEOL is made with two NbN routing layers connected through planarized Nb-based plug vias, made using standard damascene techniques with a two step chemical mechanical polishing. Wafer-level parametric tests are used to assess the quality of the technology at room temperature and die-level low temperature electrical measurements in a cryostat are performed to evaluate the BEOL and more specifically the via superconducting properties. The vias are characterized with a critical temperature ≥ 6.4 K, a critical magnetic field of ≈ 3.6 T and a critical current of 9.6 mA at 2 K and 0 T was evaluated for a 25x25 via array. Additionally, low temperature radio-frequency measurements at 9 K validate the stability of the via resistance up to a few GHz.
Scaling of solid-state quantum bits requires more and more complex connectivity schemes within two- or three-dimensional architectures. In that context, superconducting interconnects appear essential to tackle the associated challenges of compactness, thermal management and signal dispersion. We report on the fabrication of a two-level superconducting backend-of-line (BEOL) using 200 mm Si wafer technologies. This BEOL is made with two NbN routing layers connected through planarized Nb-based plug vias, made using standard damascene techniques with a two step chemical mechanical polishing. Wafer-level parametric tests are used to assess the quality of the technology at room temperature and die-level low temperature electrical measurements in a cryostat are performed to evaluate the BEOL and more specifically the via superconducting properties. The vias are characterized with a critical temperature ≥ 6.4 K, a critical magnetic field of ≈ 3.6 T and a critical current of 9.6 mA at 2 K and 0 T was evaluated for a 25x25 via array. Additionally, low temperature radio-frequency measurements at 9 K validate the stability of the via resistance up to a few GHz.
Abstract To reach large-scale quantum computing, three-dimensional integration of scalable qubit arrays and their control electronics in multi-chip assemblies is promising. Within these assemblies, the use of superconducting interconnections, as routing layers, offers interesting perspectives in terms of (1) thermal management to protect the qubits from control electronics self-heating, (2) passive device performance with significant increase of quality factors and (3) density rise of low and high frequency signals thanks to minimal dispersion. We report on the fabrication, using 200 mm silicon wafer technologies, of a multi-layer routing platform designed for the hybridization of spin qubit and control electronics chips. A routing level couples the qubits and the control circuits through one layer of Al 0.995 Cu 0.005 and superconducting layers of TiN, Nb or NbN, connected between them by W-based vias. Wafer-level parametric tests at 300 K validate the yield of these technologies while low temperature electrical measurements in cryostat are used to extract the superconducting properties of the routing layers. Preliminary low temperature radio-frequency characterizations of superconducting passive elements, embedded in these routing levels, are presented.
Using a fully automated cryogenic wafer prober, we measured superconductor fabrication process control monitors and simple integrated circuits on 200-mm wafers at 4.4 K, including SQIF-based magnetic field sensors, SQUID-based circuits for measuring inductors, Nb/Al-AlOx/Nb Josephson junctions, test structures for measuring critical current of superconducting wires and vias, resistors, etc., to demonstrate the feasibility of using the system for characterizing niobium superconducting devices and integrated circuits on a wafer scale. Data on the wafer-scale distributions of the residual magnetic field, junction tunnel resistance, energy gap, inductance of multiple Nb layers, and critical currents of interlayer vias are presented. A comparison with existing models is made. The wafers were fabricated in the SFQ5ee process, the fully planarized process with eight niobium layers and a layer of kinetic inductors, developed for superconductor electronics at MIT Lincoln Laboratory, Lexington, MA, USA. The cryogenic wafer prober was developed at HPD/FormFactor, Inc., Boulder, CO, USA.
Increasing circuit complexity within quantum systems based on superconducting qubits necessitates high connectivity while retaining qubit coherence. Classical micro-electronic systems have addressed interconnect density challenges by using 3D integration with interposers containing through-silicon vias (TSVs), but extending these integration techniques to superconducting quantum systems is challenging. Here, we discuss our approach for realizing high-aspect-ratio superconducting TSVs\textemdash 10 μm wide by 20 μm long by 200 μm deep\textemdash with densities of 100 electrically isolated TSVs per square millimeter. We characterize the DC and microwave performance of superconducting TSVs at cryogenic temperatures and demonstrate superconducting critical currents greater than 20 mA. These high-aspect-ratio, high critical current superconducting TSVs will enable high-density vertical signal routing within superconducting quantum processors.
In the upcoming decades quantum technologies, especially quantum computation, will have a strong influence on industrial, technological, economic, and social progress and are, therefore, considered to be one of the key technologies. The fundamental building blocks for quantum computation are quantum bits (qubits). The superconducting platform offers one of the most promising implementations due to its monolithic character and potential for scalability. Present research around the world primarily focusses on scaling up the number of qubits, so reliable wafer-scale fabrication technologies are mandatory. In this paper, we present our recent developments on wafer-scale fabrication of superconducting quantum circuits including Josephson junctions by the Manhattan-type technology. We discuss fabrication parameters as well as electrical characterization. For arrays out of 50 Josephson junctions with structure dimensions of 200 nm × 200 nm, we achieve a critical current standard deviation of approx. 3% on-chip and 7% on-wafer. We also show first measurement results of so fabricated transmon-type qubits with relaxation and decoherence times ofT1= 12.5 µs andT2= 15.0 µs, respectively. With an increasing number of superconducting qubits and, thus, their input and read-out lines, new challenges arise: Crosstalk between qubits, unwanted modes in the qubit environment, and required interconnections. One way to counteract is the implementation of low inductance connections across coplanar waveguides. This can be realized by aluminum air bridges. In this paper we discuss the air bridges’ fabrication parameters and the impact on the integrated circuits’ elements, e.g., Josephson junctions. We show electrical and superconducting measurements with critical temperatures and critical currents ofTc> 1.0 K andIc> 0.6 mA, respectively.
We report on technique and results for superconductor electronics fabrication process, featuring customizable number of planarized superconducting layers. The novel technique enhanced yield on stackable vias of our standard planarized process (RIPPLE) by eliminating the need for an additional deposition of aluminum as an etch stop in the metal-via stack. The drawback of the previous approach was the difficulty in processing aluminum using either wet or dry etch mechanisms. Here, we discuss details of the novel fabrication process flow and its realization for 4.5 kA/cm2 fabrication process with six Nb layers with two fully planarized layers. We report test results of various planarization diagnostics structures, accounting the influence of topology on Josephson junction quality, as well as yield and critical current of via stacks. We also report on inductance measurement results providing information on interlayer dielectric thickness for planarized layers; confirming a good uniformity over the wafer. Basic components of superconducting logic such as dc/SFQ, SFQ/dc converters, Josephson transmission lines (JTLs), and simple digital circuits such as half-adder (HA) have been designed, fabricated and tested using either conventional (RSFQ) or energy-efficient (ERSFQ) approach. The ERSFQ HA cells with bias inductors fabricated in two planarized layers were shown to function with the operational margins of +/-22%.
We present the RF characterization of 2-µm-wide superconducting coplanar waveguides made of 100-nm-thick niobium (Nb) or niobium nitride (NbN) films fabricated on 200 mm silicon wafers. Measurements of the two-ports S-parameters up to 25 GHz in a 4.7K–14 K temperature range with an added direct current up to 115 mA were done using a cryogenic probe station. With proper RF calibration and de-embedding procedure, both temperature and dc current dependence of the RF superconducting properties are analyzed. We report a kinetic inductance of 0.15 pH/□, a critical current density of 50 MA/cm2, and a critical temperature of 8.9 K for Nb as well as 4.27 pH/□, 3 MA/cm2, and 13.8 K for NbN. A telegraphist transmission line model taking into account the BCS theory has been developed and the comparison with the measurements is discussed.