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Advanced Quantum Technologies

Parallel Flagged Fault‐tolerant Error Correction for Stabilizer Codes of Distance 5

Chao Du, Zhi Ma, Yiting Liu, Qianheng Duan, Yangyang Fei

Published Mar 22, 2024• 3 citations
Publisher

Abstract

Abstract Flagged fault‐tolerant error correction schemes have attracted a lot of attention for their low qubit overhead, but usually require a high circuit depth. One way to reduce the depth is to develop parallel flagged syndrome extraction circuits. This study investigates parallel syndrome extraction circuits for Calderbank‐Shor‐Steane codes with distance 5. A simple algorithm for finding parallel flagged syndrome extraction circuits is provided. Using this algorithm, the parallel flagged circuits of the [[17,1,5]] and [[19,1,5]] color codes are constructed precisely. The error pseudo‐thresholds for code schemes are also precisely simulated and calculated. The parallel scheme in this study, based on the [[17,1,5]] and [[19,1,5]] color codes, outperforms traditional flagged schemes, particularly when the idle location error rate is high.

DOI
10.1002/qute.202300291

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Abstract Flagged fault‐tolerant error correction schemes have attracted a lot of attention for their low qubit overhead, but usually require a high circuit depth. One way to reduce the depth is to develop parallel flagged syndrome extraction circuits. This study investigates parallel syndrome extraction circuits for Calderbank‐Shor‐Steane codes with distance 5. A simple algorithm for finding parallel flagged syndrome extraction circuits is provided. Using this algorithm, the parallel flagged circuits of the [[17,1,5]] and [[19,1,5]] color codes are constructed precisely. The error pseudo‐thresholds for code schemes are also precisely simulated and calculated. The parallel scheme in this study, based on the [[17,1,5]] and [[19,1,5]] color codes, outperforms traditional flagged schemes, particularly when the idle location error rate is high.
Given that quantum error correction processes are unreliable, an efficient error syndrome extraction circuit should use fewer ancillary qubits, quantum gates, and measurements, while maintaining low circuit depth, to minimizing the circuit area, roughly defined as the product of circuit depth and the number of physical qubits. We propose to design parallel flagged syndrome extraction with shared flag qubits for quantum stabilizer codes. Versatile parallelization techniques are employed to minimize the required circuit area, thereby improving the error threshold and overall performance. Specifically, measurement outcomes across multiple rounds of syndrome extraction are integrated into a lookup table decoder, enabling parallelization of multiple stabilizer measurements with shared flag qubits. Additionally, we introduce an adaptive technique to reduce the overhead from excessive syndrome extraction. We present flag-sharing and fully parallel schemes for the[ ⁣[17,1,5] ⁣][\![17,1,5]\!][[17,1,5]],[ ⁣[19,1,5] ⁣][\![19,1,5]\!][[19,1,5]]Calderbank-Shor-Steane (CSS) codes and the[ ⁣[5,1,3] ⁣][\![5,1,3]\!][[5,1,3]]non-CSS code, where the[ ⁣[5,1,3] ⁣][\![5,1,3]\!][[5,1,3]]implementation achieves the minimum known circuit area. Numerical simulations have demonstrated improved pseudo-thresholds for these codes by up to an order of magnitude compared to previous schemes in the literature.
To perform achieve fault-tolerant quantum computation, one can use flagged syndrome extraction with fewer ancilla qubits. However, it suffers from long circuit depth if one stabilizer is measured at a time. Previously, Reichardt showed that it is possible to measure multiple stabilizers with at most one shared flag qubit for certain small quantum codes. In this paper, we propose a procedure for general Calderbank-Shor-Steane codes of distance three so that multiple ZZZ stabilizers (XXX stabilizers) can be fault tolerantly measured in parallel with one shared flag qubit. We simulate the memory and computation pseudothresholds for various code schemes. In particular, our parallel scheme based on Shor's nine-qubit code performs better than known seven- and nine-qubit schemes in the literature.
In this work, we propose a parallel low-depth flagged syndrome extraction protocol for faulttolerant quantum error correction.The protocol combines parallel measurement of different stabilizers with dynamic selection of a minimal stabilizer set, guided by flag outcomes.Circuit-level optimizations, including CNOT reordering, are integrated while rigorously preserving fault-tolerance guarantees.Implementations for several distance-3 and distance-5 codes achieve substantial reductions in circuit depth and idle locations.Numerical simulations under a circuit-level depolarizing noise model demonstrate consistent pseudo-threshold improvements, such as 12.56% and 4.43% over prior schemes for [[5, 1, 3]], 16.2% for [[7, 1, 3]], and 14.55% to 30.13% for distance-5 codes, confirming the effectiveness of the cooptimized approach.This co-optimized framework offers a practical pathway towards more resource-efficient fault-tolerant quantum computation.
In this work, we present a low-depth flagged syndrome extraction strategy for Calderbank-Shor-Steane (CSS) codes of distance 3. We demonstrate that if one stabilizer generator of a distance-3 CSS code measured using the flagged circuit has and only has two distinct qubit supports with certain stabilizers of opposite types, then the number of stabilizers required for the second round of measurements can be reduced. The number of these stabilizers depends on the weight of the measured generator. This novel strategy utilizes past syndrome information and elements from the stabilizer group, enabling the implementation of a flag-FTEC protocol for distance-3 CSS codes with lower-depth syndrome extraction circuits compared to previously flag fault-tolerant protocol if the total weight of these stabilizers is less than that of stabilizer generators. Based on our strategy, we also improve the flag-FTEC protocol for cyclic CSS codes of distance 3, which requires fewer stabilizer measurements. We utilize the[[14,2,3]][[{14,2,3}]][[14,2,3]]CSS code,[[15,1,3]][[{15,1,3}]][[15,1,3]]quantum Reed-Muller code and[[15,7,3]][[{15,7,3}]][[15,7,3]]cyclic CSS code to demonstrate how the strategy operates. Furthermore, we also provide a low-depth flagged syndrome extraction strategy for a[[19,1,5]][[{19,1,5}]][[19,1,5]]CSS-type code.
Flag qubits have recently been proposed in syndrome extraction circuits to detect high-weight errors arising from fewer faults. The use of flag qubits allows the construction of fault-tolerant protocols with the fewest number of ancillas known to date. In this work, we prove some critical properties of Calderbank-Shor-Steane (CSS) codes constructed from classical cyclic codes that enable the construction of a flag fault-tolerant error correction scheme. We then develop fault-tolerant protocols as well as a family of circuits for flag fault-tolerant error correction and operator measurement, requiring only four ancilla qubits and applicable to cyclic CSS codes of distance 3. The measurement protocol can be further used for logical Clifford gate implementation via quantum gate teleportation. We also provide examples of cyclic CSS codes with large encoding rates.