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arXiv:2407.00607 · IEEE Transactions on Quantum Engineering

Reducing Quantum Error Correction Overhead With Versatile Flag-Sharing Syndrome Extraction Circuits

Pei-Hao Liou, Ching–Yi Lai

Published Jan 1, 2025• 5 citations
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Abstract

Given that quantum error correction processes are unreliable, an efficient error syndrome extraction circuit should use fewer ancillary qubits, quantum gates, and measurements, while maintaining low circuit depth, to minimizing the circuit area, roughly defined as the product of circuit depth and the number of physical qubits. We propose to design parallel flagged syndrome extraction with shared flag qubits for quantum stabilizer codes. Versatile parallelization techniques are employed to minimize the required circuit area, thereby improving the error threshold and overall performance. Specifically, measurement outcomes across multiple rounds of syndrome extraction are integrated into a lookup table decoder, enabling parallelization of multiple stabilizer measurements with shared flag qubits. Additionally, we introduce an adaptive technique to reduce the overhead from excessive syndrome extraction. We present flag-sharing and fully parallel schemes for the$[\![17,1,5]\!]$,$[\![19,1,5]\!]$Calderbank-Shor-Steane (CSS) codes and the$[\![5,1,3]\!]$non-CSS code, where the$[\![5,1,3]\!]$implementation achieves the minimum known circuit area. Numerical simulations have demonstrated improved pseudo-thresholds for these codes by up to an order of magnitude compared to previous schemes in the literature.

DOI
10.1109/tqe.2025.3572764

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Given that quantum error correction processes are unreliable, an efficient error syndrome extraction circuit should use fewer ancillary qubits, quantum gates, and measurements, while maintaining low circuit depth, to minimizing the circuit area, roughly defined as the product of circuit depth and the number of physical qubits. We propose to design parallel flagged syndrome extraction with shared flag qubits for quantum stabilizer codes. Versatile parallelization techniques are employed to minimize the required circuit area, thereby improving the error threshold and overall performance. Specifically, measurement outcomes across multiple rounds of syndrome extraction are integrated into a lookup table decoder, enabling parallelization of multiple stabilizer measurements with shared flag qubits. Additionally, we introduce an adaptive technique to reduce the overhead from excessive syndrome extraction. We present flag-sharing and fully parallel schemes for the[ ⁣[17,1,5] ⁣][\![17,1,5]\!][[17,1,5]],[ ⁣[19,1,5] ⁣][\![19,1,5]\!][[19,1,5]]Calderbank-Shor-Steane (CSS) codes and the[ ⁣[5,1,3] ⁣][\![5,1,3]\!][[5,1,3]]non-CSS code, where the[ ⁣[5,1,3] ⁣][\![5,1,3]\!][[5,1,3]]implementation achieves the minimum known circuit area. Numerical simulations have demonstrated improved pseudo-thresholds for these codes by up to an order of magnitude compared to previous schemes in the literature.
To perform achieve fault-tolerant quantum computation, one can use flagged syndrome extraction with fewer ancilla qubits. However, it suffers from long circuit depth if one stabilizer is measured at a time. Previously, Reichardt showed that it is possible to measure multiple stabilizers with at most one shared flag qubit for certain small quantum codes. In this paper, we propose a procedure for general Calderbank-Shor-Steane codes of distance three so that multiple ZZZ stabilizers (XXX stabilizers) can be fault tolerantly measured in parallel with one shared flag qubit. We simulate the memory and computation pseudothresholds for various code schemes. In particular, our parallel scheme based on Shor's nine-qubit code performs better than known seven- and nine-qubit schemes in the literature.
In this work, we propose a parallel low-depth flagged syndrome extraction protocol for faulttolerant quantum error correction.The protocol combines parallel measurement of different stabilizers with dynamic selection of a minimal stabilizer set, guided by flag outcomes.Circuit-level optimizations, including CNOT reordering, are integrated while rigorously preserving fault-tolerance guarantees.Implementations for several distance-3 and distance-5 codes achieve substantial reductions in circuit depth and idle locations.Numerical simulations under a circuit-level depolarizing noise model demonstrate consistent pseudo-threshold improvements, such as 12.56% and 4.43% over prior schemes for [[5, 1, 3]], 16.2% for [[7, 1, 3]], and 14.55% to 30.13% for distance-5 codes, confirming the effectiveness of the cooptimized approach.This co-optimized framework offers a practical pathway towards more resource-efficient fault-tolerant quantum computation.
Abstract Flagged fault‐tolerant error correction schemes have attracted a lot of attention for their low qubit overhead, but usually require a high circuit depth. One way to reduce the depth is to develop parallel flagged syndrome extraction circuits. This study investigates parallel syndrome extraction circuits for Calderbank‐Shor‐Steane codes with distance 5. A simple algorithm for finding parallel flagged syndrome extraction circuits is provided. Using this algorithm, the parallel flagged circuits of the [[17,1,5]] and [[19,1,5]] color codes are constructed precisely. The error pseudo‐thresholds for code schemes are also precisely simulated and calculated. The parallel scheme in this study, based on the [[17,1,5]] and [[19,1,5]] color codes, outperforms traditional flagged schemes, particularly when the idle location error rate is high.
Flag-style fault-tolerance has become a linchpin in the realization of small fault-tolerant quantum-error correction experiments. The flag protocol's utility hinges on low qubit over-head, which is typically much smaller than in other approaches. However, as in most fault-tolerance protocols, the advantages of flag-style error correction come with a tradeoff: fault tolerance can be guaranteed, but such protocols involve high-depth circuits, due to the need for repeated stabilizer measurements. Here, we demonstrate that a dynamic choice of stabilizer measurements, based on past syndromes, and the utilization of elements from the full stabilizer group, leads to flag protocols with lower-depth syndrome-extraction circuits for the [[5], [1], [3]] code, as well as for the Steane code when compared to the standard methods in flag fault tolerance. We methodically prove that our new protocols yield fault-tolerant lookup tables, and demonstrate them with a pseudothreshold simulation, showcasing large improvements for all protocols when compared to previously-established methods. This work opens the dialogue on exploiting the properties of the full stabilizer group for reducing circuit overhead in fault-tolerant quantum-error correction.
Reliable quantum computation requires fault-tolerant protocols to prevent errors from propagating during syndrome extraction in quantum error correction. We present a novel fault-tolerant syndrome extraction technique for CSS codes, which we refer to as the cut-cat state scheme. While each ancilla qubit interacts non-fault-tolerantly with a pair of data qubits, we introduce additional cat stabilizer measurements to identify and correct the resulting hook errors. Our approach maintains the key benefit of cat-based extraction, i.e., parallelized data qubit interactions, while reducing the number of simultaneous qubits required by more than half. Compared to flag-based state-of-the-art protocols, the cut-cat scheme offers a notable advantage in terms of two-qubit gate count as the code distance increases.
Device error rates on current quantum computers have improved enough to where demonstrations of error correction below break even are now possible. Still, the circuits required for quantum error correction introduce significant overhead and sometimes inject more errors than they correct. In this work, we introduce adaptive syndrome extraction as a scheme to improve code performance and reduce the quantum error-correction cycle time by measuring only the stabilizer generators that are likely to provide useful syndrome information. We provide a concrete example of the scheme through the [[4,2,2]] code concatenated with a hypergraph product code and a syndrome-extraction cycle that uses quantum error detection to modify the syndrome-extraction circuits in real time. Compared to nonconcatenated codes and nonadaptive syndrome extraction, we find that the adaptive scheme achieves over an order of magnitude lower logical error rates while requiring fewer gates and physical qubits. Furthermore, we show how to achieve fault-tolerant universal logical computation with [[4,2,2]]-concatenated hypergraph product codes.