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IEEE Access

A Low-Latency Dual-Path QC-LDPC Decoder for IEEE 802.11ax

Yujun Wu, Bin Wu

Published Jan 1, 2024• 0 citations
Publisher

Abstract

Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes have been widely adopted to achieve excellent error correction performance in many wireless communication systems. The growing use of QC-LDPC codes calls for a low-latency and low-complexity decoder architecture that can be used in practical baseband chips. This paper presents a fully compatible low-latency LDPC decoder for IEEE 802.11ax. In contrast to the traditional partially parallel structure, such as the row parallel or block serial, we propose a scheme to realize the parallel of double blocks with few stall cycles. The first part of the strategy is to obtain the optimal sub-matrix prototypes, Hp1, Hp2, and corresponding access order offline. The second part is to decode according to the specified order. Besides, the related pipelined successive processing hardware is also designed with a memory bypass strategy. The proposed decoder is implemented in a 55 nm process with 482K logic gates, a throughput of 2132 Mbps, and a single iteration clock cycle of 45-63. Compared to other decoders with similar parallelism, this decoder stands out in terms of latency, hardware complexity, and energy efficiency.

DOI
10.1109/access.2023.3247958

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Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes have been widely adopted to achieve excellent error correction performance in many wireless communication systems. The growing use of QC-LDPC codes calls for a low-latency and low-complexity decoder architecture that can be used in practical baseband chips. This paper presents a fully compatible low-latency LDPC decoder for IEEE 802.11ax. In contrast to the traditional partially parallel structure, such as the row parallel or block serial, we propose a scheme to realize the parallel of double blocks with few stall cycles. The first part of the strategy is to obtain the optimal sub-matrix prototypes, Hp1, Hp2, and corresponding access order offline. The second part is to decode according to the specified order. Besides, the related pipelined successive processing hardware is also designed with a memory bypass strategy. The proposed decoder is implemented in a 55 nm process with 482K logic gates, a throughput of 2132 Mbps, and a single iteration clock cycle of 45-63. Compared to other decoders with similar parallelism, this decoder stands out in terms of latency, hardware complexity, and energy efficiency.
Low-Density Parity-Check (LDPC) codes have traditionally performed better at longer code lengths. This research develops and rigorously evaluates a layered Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture intended for Ultra-Reliable Low-Latency Communication (URLLC) applications in 5G and subsequent technologies. The paper investigates LDPC codes in short-length contexts through architectural optimization based on a layered decoding approach, which provides improved convergence speed and reduced latency compared with traditional flooding techniques. The short block-length QC-LDPC code (280,176) addresses the dual challenge of achieving ultra-low latency while maintaining high performance relative to existing work. For a target BLER of 10−2, the decoder outperforms the shorter reference codes (60,40) and (96,64), with an Eb/N0 gain of up to 0.9 dB, part of which is attributable to the longer block length rather than to the decoder alone. The FPGA implementation results demonstrate that the design is hardware-efficient: it operates at a maximum frequency of 218.62 MHz, resulting in a throughput of 155.77 Mbps, while maintaining a decoding latency of only 1.129 µs and a power consumption of 0.201 W.
This paper studies low-complexity high-speed decoder architectures for quasi-cyclic low density parity check (QC-LDPC) codes. Algorithmic transformation and architectural level optimization are incorporated to reduce the critical path. Enhanced partially parallel decoding architectures are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing a small percentage of extra hardware. Based on the proposed architectures, a (8176, 7154) Euclidian geometry-based QC-LDPC code decoder is implemented on Xilinx field programmable gate array (FPGA) Virtex-II 6000, where an efficient nonuniform quantization scheme is employed to reduce the size of memories storing soft messages. FPGA implementation results show that the proposed decoder can achieve a maximum (source data) decoding throughput of 172 Mb/s at 15 iterations
Low-density parity-check (LDPC) codes are one of the most effective error controlling methods, which now are widely used in multiple communication systems, for example, DVB-S2, 802.16e, etc. In these communication standards, the adopted LDPC codes are all quasi-cyclic low-density parity-check (QC-LDPC) codes. The parity-check matrices of QC-LDPC codes consist of arrays of circulants, in which each row is the cyclic shift of the row above it, and the first row is the cyclic shift of the last row. This character of QC-LDPC codes results in the linear encoding complexity and opens the door for the multi-mode LDPC decoders with enough flexibility of resource multiplexing. Based on the quasi-cyclic character of QC-LDPC codes, a design method for multi-mode QC-LDPC decoders is proposed in this paper. The node memory is skillfully organized and can be expediently addressed by a simple control unit to save memory consumption in hardware implementation. Then this design method is implemented and test on Field Programmable Gate Array (FPGA) platform. The test results show that the resource occupied by the multi-mode decoder is only a little more than that of maximal resource occupied by the single-mode decoder, and this multi-mode decoder can support at least 3 code rates with the throughput higher than 100 Mbps when the iteration number is fixed to 12 and the clock frequency is set to 200 MHZ.
In this paper, design of a high throughput low-density parity-check (LDPC) decoder using overlapped message passing scheduling algorithm is presented. Regular hierarchical quasi-cyclic (H-QC) LDPC code is used in this design to provide good coding performance at long code length. The two-level regular H-QC LDPC code matrix structure is exploited to parallelize the row and column decoding operations. Our scheduling algorithm re-arranges these operations across iteration boundaries to avoid memory access conflicts. The memory requirement is reduced by half compared to pipelined decoders without scheduling. A (12288, 6144) LDPC decoder implemented in FPGA achieves 298 Mbps throughput performance.
A novel flexible decoding architecture for quasi-cyclic (QC) low-density parity-check (LDPC) code is proposed in this paper to reduce decoding complexity. The novelty of this architecture lies in a new time-sharing scheme of processing units, which provides low complexity and flexible serial factor of decoding hardware. Without loss of coding performance, the architecture requires significantly less processing units compared with known semi-parallel decoders at the expense of throughput decrease, while keeping memory requirement unchanged. As demonstrated by hardware and software implementation results, the proposed architecture is advisable and competent for wireless mobile systems and portable devices.
In this paper, the authors propose an efficient highly-parallel decoder architecture using partially overlapped decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes, which leads to reduction in hardware complexity and power consumption. Generally, due to the regularly structured parity-check matrix H of QC LDPC codes, the message updating computations in the check node unit (CNU) and the variable node unit (VNU) can be efficiently overlapped, which increases the decoding throughput by maximizing the hardware utilization efficiency (HUE). However, the partially overlapped decoding scheme cannot be used to design a highly-parallel decoding architecture for high-throughput applications. For (3, 5)-regular QC LDPC codes, our proposed method could reduce the hardware complexity by approximately 33% for the CNU and 20% for the VNU in the highly-parallel decoder architecture without any performance degradation. In addition, the power consumption can be minimized by reducing the total number of memory accesses for updated messages.