It is expected that a useful quantum computing (QC) system would require millions of qubits within one system. The state-of-the-arts QC systems contain hundreds of qubits, which is still several orders of magnitude away from the ultimate goal. To scale the QC system, namely, to increase the number of qubits and QC circuit layers, and also to improve the performance such as fidelity, robustness, etc., we need to develop scalable techniques including high-density qubit devices, ultra-low power qubit interfacing circuits, 3D interconnection and packaging etc. This article will review the recent reported device, circuit and system-level techniques that contribute to the QC system scaling and may ultimately lead to a fully functional quantum computer.
It is expected that a useful quantum computing (QC) system would require millions of qubits within one system. The state-of-the-arts QC systems contain hundreds of qubits, which is still several orders of magnitude away from the ultimate goal. To scale the QC system, namely, to increase the number of qubits and QC circuit layers, and also to improve the performance such as fidelity, robustness, etc., we need to develop scalable techniques including high-density qubit devices, ultra-low power qubit interfacing circuits, 3D interconnection and packaging etc. This article will review the recent reported device, circuit and system-level techniques that contribute to the QC system scaling and may ultimately lead to a fully functional quantum computer.
Quantum computers are domain-specific accelerators that can solve commercially important problems that are beyond the capability of conventional computers. Quantum computing is at an inflection point where small systems with a few dozen qubits have been demonstrated and the number of qubits is expected to increase to several hundred over the coming years. However, the qubit quality is likely to remain quite low making it difficult to execute programs reliably. Furthermore, scaling the designs to a large number of qubits would require specialized hardware that operates at cryogenic conditions. This article describes the compiler and hardware support for enabling reliable and scalable quantum computers.
For the realization of a quantum computer, a good qubit design as the basic building block is a nontrivial starting point. To fully leverage the potential of quantum computing, quantum processors will likely have to incorporate billions of high-quality qubits. Several approaches are being pursued and exhibit different strength and weaknesses. The device concepts and fabrication procedures for semiconductor based qubits are very similar to those used in the semiconductor industry. Using the spin-degree of freedom, their coherence properties and the quality of single-qubit operations have now reached the required level and are on par with competing approaches. Two-qubit operations will likely follow suit in the near future. With these basic requirements being met, it is now time to think if and how increasingly large multi-qubit systems and eventually functional quantum processor can be realized. This quest raises many pertinent questions, some of which equally apply to other qubit platforms. How reproducibly can the different types of semiconductor qubits be produced? How can their operating point be adjusted efficiently and in an automated way? How can they be connected to form meaningful multi-qubit circuits? How severe are multi-qubit control issues such as crosstalk and frequency crowding, and how can they be avoided? What control system architectures are most suitable for operating large numbers of qubits? What is the limit of cryogenic electronics regarding power consumption and integration density? This paper gives a (partial) overview of the state of the art in the field and discusses future challenges associated with the realization of large-scale quantum processors, many of which will greatly benefit from input from engineering science. The guiding vision is that of a highly integrated quantum processor with an ultra-low power cryogenic control system.
Quantum computing (QC) is expected to extend the high performance computing roadmap [1]-[2] at the condition to be able to run a large number of errorless quantum operations, typically. over a billion. It is out of reach in actual physical systems because of the quantum decoherence. As a consequence, quantum error correction techniques, which utilize the idea of redundant encoding, have been introduced to cure for the errors [3]-[5]. In state-of-the-art codes, with error thresholds or fidelities around 10-2in Si spin qubits, it is expected that logical qubits will be made out of a few thousands or more of physical qubits [6], bringing the number of required physical qubits to perform relevant quantum calculations to at least a million.
Quantum computers have gained widespread interest as they can potentially solve problems that are intractable even for today’s supercomputers, such as the simulation of quantum systems as initially proposed by Feynman. To achieve such tremendous progress, a quantum computer relies on processing the information stored in quantum bits (qubits), the fundamental units of quantum computation, similar to the bits in a classical (i.e., non-quantum) processor. In general, a quantum processor comprising several qubits is connected through a quantum-to-classical interface consisting of classical electrical circuits for manipulating and reading out their quantum state. The accuracy of an operation on a qubit is characterized using the fidelity, which is 100 % in case of a perfect operation. In practice, a fidelity between 99 % and 99.9 % is typically achieved in today’s experiments with less than 100 qubits, limited by non-idealities in the control signals and by the implementation of the physical qubit itself. Since such qubit fidelities are too low to execute relevant quantum algorithms, quantum error correction schemes have been developed which rely on a much larger number of qubits to correct for possible errors, resulting in the need for quantum processors with thousands or millions of qubits. Solid-state qubits promise the largescale integration required to scale to millions of qubits, as they exploit the lithographic fabrication techniques borrowed from the semiconductor industry. However, state-of-theart solid-state qubits, such as transmons and single-electron spin qubits, must be typically cooled to cryogenic temperatures in a dilution refrigerator to exhibit quantum behavior. Because of the limited number of qubits (< 100) in state-of-theart solid-state quantum processors, the classical controller is currently implemented by general-purpose instruments or by tailor-made controllers operating at room temperature connected via several wires to the qubits in the cryogenic chamber. However, these systems must scale to support millions of qubits. While scaling up the underlying quantum processor is already exceptionally challenging, building the electronics required to interface such a large-scale processor is just as relevant and arduous.
As a key approach to augment Moores Law scaling, 3D integration technologies have enabled small form factor, low cost, diverse, modular and flexible assembly of integrated circuits in the semiconductor industry. It is therefore essential to adopt these technologies to the quantum computing devices which are at the nascent stage and generally require large scale integration to be particle. In this review, we focus on four popular quantum bit (qubit) candidates (trapped ion, superconducting circuit, silicon spin and photon) which are encoded by distinct physical systems but all intrinsically compatible with advanced CMOS fabrication process. We introduce the specific scalability bottlenecks of each qubit type and present the current solutions using 3D integration technologies. We evaluate and classify these technologies into three main categories based on the hierarchy. A brief discussion regarding to the thermal management is also provided. We believe this review serves to provide some useful insights on the contributions of interconnect, integration and packaging to the field of quantum computing where rapid development is ongoing.
In the span of four decades, quantum computation has evolved from an intellectual curiosity to a potentially realizable technology. Today, small-scale demonstrations have become possible for quantum algorithmic primitives on hundreds of physical qubits. Nevertheless, there are significant outstanding challenges in quantum hardware, fabrication, software architecture, and algorithms on the path towards a full-stack scalable quantum computing technology. Here, we provide a comprehensive review of these scaling challenges. We show how to facilitate scaling by adopting existing semiconductor technology to build much higher-quality qubits, employing systems engineering approaches, and performing distributed heterogeneous quantum-classical computing. We provide a detailed resource and sensitivity analysis for quantum applications on surface-code error-corrected quantum computers given current, target, and desired hardware specifications based on superconducting qubits, accounting for a realistic distribution of errors. We provide comprehensive resource estimates for several utility-scale applications including quantum chemistry calculations, catalyst design, NMR spectroscopy, and Fermi-Hubbard simulation. We show that orders of magnitude enhancement in performance could be obtained by a combination of hardware improvements and tight quantum-HPC integration. Furthermore, we introduce high-performance architectures for quantum-probabilistic computing with custom-designed accelerators to tackle today's industry-scale classical optimization, machine learning, and quantum simulation tasks in a cost-effective manner.