Timing Evaluation of Passive Transmission Line by RSFQ Ring Oscillator

Abstract

Passive transmission line (PTL) has been widely applied in rapid single flux quantum (RSFQ) circuits, especially as the first choice of long-distance transmission in large-scale integrated circuits such as arithmetic and logic unit (ALU) and central processing unit (CPU). With the increasing demand of timing regulation, general bias margin is not enough to evaluate the performance of PTL circuits. Timing accuracy including propagation delay of the micro stripe line (MSL) and its delay skew is more critical for clock routine and signal transmission when employing PTL circuits. However, the related reports about the timing information of PTL circuits is limited in the single-value verification of the theoretical MSL's delay. More factors such as bias current, transmission length and system noise should be considered into the evaluation of the PTL circuits. This work focuses on the timing extraction of the designed PTL circuits through different control groups, and evaluates the timing discrepancy between the measurement and simulation. We adopt the method of time accumulation by increasing different lengths of MSL in the loop of the ring oscillator (RO) and subtract each other to evaluate the MSL's propagation delay. We analyzed MSLs of two layers (MSL1 and MSL2). The measured propagation delay of 1${\bm{mm}}$MSL is 8.20${\bm{ps}}/{\bm{mm}}\ $for MSL1 and 7.66${\bm{ps}}/{\bm{mm}}$for MSL2, which has a delay skew of 0.30${\bm{ps}}$and 0.57${\bm{ps}}$from the simulated value (8.23${\bm{ps}}$). Within MSL transmission length of 5${\bm{mm}}$, a maximum deviation of 1.2${\bm{ps}}$is adopted as time redundancy of PTL circuits applied in ALU and CPU design.