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IEEE Transactions on Applied Superconductivity

High frequency operation of JTL ring oscillator with a passive transmission line

Hideo Suzuki, Shuichi Nagasawa, H. Hasegawa, T. Hashimoto, Kazunori Miyahara, Yûji Enomoto

Published Mar 1, 2001• 5 citations
Publisher

Abstract

We have designed ring oscillators to test rapid single flux quantum (RSFQ) circuits with passive transmission lines at high frequencies. To reduce the width of the transmission line, design methods for increasing the characteristic impedance of the transmission line have been investigated and then we designed a 5-stage of Josephson transmission line (JTL) receiver which can transform the impedance from 1 to 4 /spl Omega/ by changing the critical current and the inductance. The receiver, driver, and micro-strip line were inserted in a ring oscillator. The ring oscillator fabricated with the Nb/AlOx/Nb junction process was successfully operated at frequencies ranging from 6 to 10 GHz for line lengths of 0.6, 3, 6, and 9 mm. The usefulness of the impedance transformation was then confirmed experimentally. A propagation delay per unit length of 8.4 ps/mm was also obtained.

DOI
10.1109/77.919535

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We have designed ring oscillators to test rapid single flux quantum (RSFQ) circuits with passive transmission lines at high frequencies. To reduce the width of the transmission line, design methods for increasing the characteristic impedance of the transmission line have been investigated and then we designed a 5-stage of Josephson transmission line (JTL) receiver which can transform the impedance from 1 to 4 /spl Omega/ by changing the critical current and the inductance. The receiver, driver, and micro-strip line were inserted in a ring oscillator. The ring oscillator fabricated with the Nb/AlOx/Nb junction process was successfully operated at frequencies ranging from 6 to 10 GHz for line lengths of 0.6, 3, 6, and 9 mm. The usefulness of the impedance transformation was then confirmed experimentally. A propagation delay per unit length of 8.4 ps/mm was also obtained.
Along with the improvement of integration and the requirement of high-speed operation, the passive transmission line (PTL) plays a significant role in superconducting integrated circuits due to its intrinsic advantage of extremely low propagation delay and low signal loss in long-distance transmission. Good impedance matching is critical to reduce the signal reflection in the transmission line and maximize the power transferred. Based on the PTL wiring layer selection under SIMIT-Nb03 process, we studied the equivalent input/output impedance for Josephson junction (JJ) at the IO port and explored a method of impedance matching in rapid-single-flux-quantum circuits by adjusting the Stewart McCumber parameterβC{\beta }_{\bm{C}}βC​of the JJ in the design of the PTL's driver and receiver. Furthermore, the accompanying influence from JJ's modifiedβC{\beta }_{\bm{C}}βC​on the performance of the driver and receiver is evaluated to maximize the profit of the functional circuits. The common-used serial resistor is removed to obtain a balanced bias margin for the PTL circuits. The proposed PTL has been designed and tested based on SIMIT-Nb03 fabrication process. In total,$ \pm $30% bias margin for the PTL is achieved at low frequency and high frequency (40 GHz) contrast tests, including operation speed and transmission length as test vector. Additionally, a frequency sweep for 1 mm PTL is performed by the designed ring oscillator on the chip. The maximum working frequency is up to 129 GHz, with a margin duration of 8%.
The increasing complexity of modern rapid single flux quantum (RSFQ) circuits has made on-chip signal routing, an issue of growing importance. In this paper, several methods for routing large-scale RSFQ circuits are described, and a process is presented for determining when to use passive microstrip transmission lines (PTL) and active Josephson transmission lines (JTL). The effect of the size of the JTL inductor and Josephson junctions on the length of a JTL chain for a target delay is also discussed. The dependence of the JTL inductance on the physical layout is evaluated, and the effects of the primary PTL parameters on delay are characterized. A novel PTL driver and receiver configuration is also proposed. Tradeoffs among the number of JJs, inductance, and length of a PTL stripline in the receiver and driver circuits are reported. The energy dissipation is evaluated for two different interconnects. A tradeoff between the proposed PTL circuits and an optimized JTL in terms of energy dissipation and delay is discussed. Guidelines for choosing the optimal element values are determined, and a simulated bias margin of ±29% for the bias current of the proposed receiver operating at 20 GHz in a 10 kA/cm2technology for a 1-mm transmission line is achieved. Summarizing, guidelines and design tradeoffs appropriate for automated layout and synthesis are provided for driving long interconnect in SFQ VLSI circuits.
Passive transmission line (PTL) has been widely applied in rapid single flux quantum (RSFQ) circuits, especially as the first choice of long-distance transmission in large-scale integrated circuits such as arithmetic and logic unit (ALU) and central processing unit (CPU). With the increasing demand of timing regulation, general bias margin is not enough to evaluate the performance of PTL circuits. Timing accuracy including propagation delay of the micro stripe line (MSL) and its delay skew is more critical for clock routine and signal transmission when employing PTL circuits. However, the related reports about the timing information of PTL circuits is limited in the single-value verification of the theoretical MSL's delay. More factors such as bias current, transmission length and system noise should be considered into the evaluation of the PTL circuits. This work focuses on the timing extraction of the designed PTL circuits through different control groups, and evaluates the timing discrepancy between the measurement and simulation. We adopt the method of time accumulation by increasing different lengths of MSL in the loop of the ring oscillator (RO) and subtract each other to evaluate the MSL's propagation delay. We analyzed MSLs of two layers (MSL1 and MSL2). The measured propagation delay of 1mm{\bm{mm}}mmMSL is 8.20${\bm{ps}}/{\bm{mm}}\ forMSL1and7.66for MSL1 and 7.66forMSL1and7.66{\bm{ps}}/{\bm{mm}}forMSL2,whichhasadelayskewof0.30for MSL2, which has a delay skew of 0.30forMSL2,whichhasadelayskewof0.30{\bm{ps}}and0.57and 0.57and0.57{\bm{ps}}fromthesimulatedvalue(8.23from the simulated value (8.23fromthesimulatedvalue(8.23{\bm{ps}}).WithinMSLtransmissionlengthof5). Within MSL transmission length of 5).WithinMSLtransmissionlengthof5{\bm{mm}},amaximumdeviationof1.2, a maximum deviation of 1.2,amaximumdeviationof1.2{\bm{ps}}$is adopted as time redundancy of PTL circuits applied in ALU and CPU design.
As the complexity of superconductor circuits grows, we envision a dense network of passive transmission lines (PTLs) being used to interconnect cells in rapid-single-flux-quantum (RSFQ) circuits. In our library approach, each cell has dedicated tracks as place holders for routing PTLs. Higher impedance PTLs are desirable due to their narrower width. However, at higher impedance, the margins for the PTL receiver degrade rapidly. We have designed, fabricated, tested, and simulated passive transmission lines (PTLs) for high-speed interconnects in the MIT-LL SFQ5ee 10 kA/cm2process. For the symmetric dual ground planes case, PTLs are in the M1 layer with M0 and M2 ground planes, or in the M3 layer with M2 and M4 ground planes. For the asymmetrical dual ground planes case, PTLs are in M2 or M3 layers with M1 and M4 ground planes. We report ±30% margins for these PTLs. We investigate the receiver margins for these PTLs and report impact of margins as a function of corners, interlayer transitions, variants of drivers, and receivers. We demonstrate 100 GHz PTL operation in ring oscillator measurements. We have also adopted multi-layer multi-conductor transmission line models for PTL simulation. We observe good model-to-hardware correlation for low- and high-frequency operation.
We report simulated results of-rapid single flux quantum (SFQ) circuits having driver, receiver, and passive transmission lines for propagating SFQ pulses to investigate the design criteria. We have studied the equivalent input/output resistance of the driver/receiver in various bias conditions and found that the resistance is almost proportional to the bias current of the driver/receiver. Furthermore, we have proposed inserting a series resistor at the end of the superconducting passive transmission line (PTL) for avoiding undesirable flux trapping in the loop and for isolation in regard to the DC current. We also found that the reduction of the bias margin due to the resistance is rather small when the resistance is much smaller than the impedance of the PTL. An operating margin of more than 30% was obtained in the driver/receiver circuits including the PTL and the series resistor.
Passive transmission lines (PTLs) provide an energy-efficient means of transporting pulsed single flux quantum (SFQ) signals between logic gates and blocks on a chip, or even between chips through a multi-chip module carrier. Although functional up to 70 GHz, our previous designs manifested sharp, length-dependent resonances resulting in diminished operating margins. These are particularly inconvenient since the resonant length is about 1 mm at 40–50 GHz, where most SFQ circuits currently function. To avoid the need to keep the PTLs < 1 mm in length, we have optimized the PTL driver-receiver pairs to sufficiently suppress these resonances; this helps facilitate the use of automated routing tools. We present experimental results, in the 10-70 GHz frequency range, for different driver-receiver pairs designed for PTLs in our dual RSFQ-ERSFQ cell library. This cell library, targeting MIT Lincoln Laboratory's SFQ5ee fabrication process, uses PTLs with two types of ground plane configuration. The first variant has signal in M1 and/or M3 with symmetrical ground planes in M0, M2 and/or M2, M4 respectively. The second variant has signal in M2 and/or M3 with asymmetrical ground planes in M1 and M4. We also present a comparison with wider, 4 Ω, PTLs that are more suitable for transport between distant logic blocks. Next, we present experimental results of PTL lengths ranging from 1.2-12 mm over the same 10-70 GHz frequency range. Finally, we report on the design of circuits for investigating crosstalk between two PTLs and their measurement results.