We have studied single-flux-quantum (SFQ) propagation properties in passive transmission lines (PTLs) based on a 10-Nb-layer device structure (ADP2). In ADP2, we can use the PTLs with a line width about 5 mum, one seventh of conventional line width by adopting a strip line (SL) structure and increasing the characteristic impedance. The evaluation has been conducted on the PTL length and the via-hole structure by using ring oscillators. We found that the decrease in the operating region was larger for longer PTL, compared with that in a conventional device structure (STD2). The results would be caused by the increase in the surface resistance. The via-holes connecting the PTLs on different layers have more complicated structure than those of STD2. We have designed the via-hole structure using the electromagnetic wave simulator HFSS. As a result, we have demonstrated sufficiently large operating margins at any data rates up to 80 Gb/s even for the ring oscillator with 30 via-holes.
We have studied single-flux-quantum (SFQ) propagation properties in passive transmission lines (PTLs) based on a 10-Nb-layer device structure (ADP2). In ADP2, we can use the PTLs with a line width about 5 mum, one seventh of conventional line width by adopting a strip line (SL) structure and increasing the characteristic impedance. The evaluation has been conducted on the PTL length and the via-hole structure by using ring oscillators. We found that the decrease in the operating region was larger for longer PTL, compared with that in a conventional device structure (STD2). The results would be caused by the increase in the surface resistance. The via-holes connecting the PTLs on different layers have more complicated structure than those of STD2. We have designed the via-hole structure using the electromagnetic wave simulator HFSS. As a result, we have demonstrated sufficiently large operating margins at any data rates up to 80 Gb/s even for the ring oscillator with 30 via-holes.
We have developed a very flexible wiring technique of passive transmission lines (PTLs) in single-flux-quantum (SFQ) circuits. For high flexibility, we introduced two types of wiring structures of strip lines (SLs) and microstrip lines (MSLs) using the fabrication process which has four metal layers. The SLs and MSLs are realized using the second and fourth metal layers as signal lines, respectively, from the bottom (the other two metal layers are used as ground planes). We also introduced via-holes for transmission between the SL and MSL. For solving the problem of impedance mismatch on complicated discontinuous sections such as joints [between the driver(receiver) and the end of SLs(MSLs)] and via-holes, we optimized the structures of these discontinuous sections and evaluated propagation properties to ensure high-speed transmission of SFQ pulses. We tested the transmission of SFQ pulses through SLs/MSLs including more than 50 via-holes, one of the most complicated lines in actual designs. We confirmed the good propagation properties of SFQ pulses up to 50 Gb/s with sufficiently wide bias margins of ±20% to be used in practical designs.
The introduction of passive-transmission-line (PTL) wiring to large-scale SFQ logic circuits offers several advantages over traditional Josephson-transmission-line (JTL) wiring, such as smaller wiring area, less delay, lower power consumption, and more freedom in routing. PTL wiring can drastically change the style of designing SFQ logic circuits. We propose a new methodology for designing large-scale SFQ circuits using PTL wiring. Aiming at generalizing SFQ circuit design, we chose synchronous clocking. We developed a placer that was suitable for SFQ circuit design to assist us with the new design methodology. The placer first synthesizes an H-tree clock distribution network, placing SFQ pulse splitter cells at each branch. It then places logic cells to minimize the maximum length of data PTL wires, aiming at higher operating speeds. Finally, a router completes the PTL wiring. To evaluate the design methodology we designed an 8-bit general purpose RISC processor. Within twelve hours, we obtained a 15-mm-square SFQ circuit that could operate up to 27.6 GHz. We adopted an advanced Nb process, which was characterized by a critical current density of 10 kA/cm2, two 5-mum-wide PTL wiring layers, and a minimum cell size of 30 mum times 30 mum. The circuit consisted of about 20,000 logic cells, which approximated more than 400,000 Josephson junctions including splitters to distribute the clock signal.
As the complexity of superconductor circuits grows, we envision a dense network of passive transmission lines (PTLs) being used to interconnect cells in rapid-single-flux-quantum (RSFQ) circuits. In our library approach, each cell has dedicated tracks as place holders for routing PTLs. Higher impedance PTLs are desirable due to their narrower width. However, at higher impedance, the margins for the PTL receiver degrade rapidly. We have designed, fabricated, tested, and simulated passive transmission lines (PTLs) for high-speed interconnects in the MIT-LL SFQ5ee 10 kA/cm2process. For the symmetric dual ground planes case, PTLs are in the M1 layer with M0 and M2 ground planes, or in the M3 layer with M2 and M4 ground planes. For the asymmetrical dual ground planes case, PTLs are in M2 or M3 layers with M1 and M4 ground planes. We report ±30% margins for these PTLs. We investigate the receiver margins for these PTLs and report impact of margins as a function of corners, interlayer transitions, variants of drivers, and receivers. We demonstrate 100 GHz PTL operation in ring oscillator measurements. We have also adopted multi-layer multi-conductor transmission line models for PTL simulation. We observe good model-to-hardware correlation for low- and high-frequency operation.
Passive transmission line (PTL) has been widely applied in rapid single flux quantum (RSFQ) circuits, especially as the first choice of long-distance transmission in large-scale integrated circuits such as arithmetic and logic unit (ALU) and central processing unit (CPU). With the increasing demand of timing regulation, general bias margin is not enough to evaluate the performance of PTL circuits. Timing accuracy including propagation delay of the micro stripe line (MSL) and its delay skew is more critical for clock routine and signal transmission when employing PTL circuits. However, the related reports about the timing information of PTL circuits is limited in the single-value verification of the theoretical MSL's delay. More factors such as bias current, transmission length and system noise should be considered into the evaluation of the PTL circuits. This work focuses on the timing extraction of the designed PTL circuits through different control groups, and evaluates the timing discrepancy between the measurement and simulation. We adopt the method of time accumulation by increasing different lengths of MSL in the loop of the ring oscillator (RO) and subtract each other to evaluate the MSL's propagation delay. We analyzed MSLs of two layers (MSL1 and MSL2). The measured propagation delay of 1mmMSL is 8.20${\bm{ps}}/{\bm{mm}}\ forMSL1and7.66{\bm{ps}}/{\bm{mm}}forMSL2,whichhasadelayskewof0.30{\bm{ps}}and0.57{\bm{ps}}fromthesimulatedvalue(8.23{\bm{ps}}).WithinMSLtransmissionlengthof5{\bm{mm}},amaximumdeviationof1.2{\bm{ps}}$is adopted as time redundancy of PTL circuits applied in ALU and CPU design.
Passive transmission lines (PTLs) provide an energy-efficient means of transporting pulsed single flux quantum (SFQ) signals between logic gates and blocks on a chip, or even between chips through a multi-chip module carrier. Although functional up to 70 GHz, our previous designs manifested sharp, length-dependent resonances resulting in diminished operating margins. These are particularly inconvenient since the resonant length is about 1 mm at 40–50 GHz, where most SFQ circuits currently function. To avoid the need to keep the PTLs < 1 mm in length, we have optimized the PTL driver-receiver pairs to sufficiently suppress these resonances; this helps facilitate the use of automated routing tools. We present experimental results, in the 10-70 GHz frequency range, for different driver-receiver pairs designed for PTLs in our dual RSFQ-ERSFQ cell library. This cell library, targeting MIT Lincoln Laboratory's SFQ5ee fabrication process, uses PTLs with two types of ground plane configuration. The first variant has signal in M1 and/or M3 with symmetrical ground planes in M0, M2 and/or M2, M4 respectively. The second variant has signal in M2 and/or M3 with asymmetrical ground planes in M1 and M4. We also present a comparison with wider, 4 Ω, PTLs that are more suitable for transport between distant logic blocks. Next, we present experimental results of PTL lengths ranging from 1.2-12 mm over the same 10-70 GHz frequency range. Finally, we report on the design of circuits for investigating crosstalk between two PTLs and their measurement results.
Abstract Interconnects are a major discriminator for superconducting digital technology, enabling energy-efficient data transfer and high-bandwidth heterogeneous integration. We report a method to simulate propagation of picosecond pulses in superconducting passive transmission lines (PTLs). A frequency-domain propagator model obtained from the Ansys high-frequency structure simulator (HFSS) field solver is incorporated in a Cadence Spectre circuit model, so that the particular PTL geometry can be simulated in the time-domain. The Mattis Bardeen complex conductivity of the superconductor is encoded in the HFSS field solver as a complex-conductivity insulator. Experimental and simulation results show that Nb 20 Ω microstrip PTLs with 200 nm interlayer dielectric thickness can support propagation of a single-flux-quantum pulse up to 7 mm and a double-flux-quantum pulse up to 28 mm.