IEEE/ACM International Symposium on Microarchitecture (MICRO)
HetArch: Heterogeneous Microarchitectures for Superconducting Quantum Systems
Samuel Stein, Sara Sussman, Teague Tomesh, Charles R. Guinn, Esin Türeci, Sophia Fuhui Lin, Wei Tang, James Ang, Srivatsan Chakram, Ang Li, Margaret Martonosi, Frederic T. Chong, Andrew Houck, Isaac L. Chuang, Michael Demarco
Noisy Intermediate-Scale Quantum Computing (NISQ) has dominated headlines in recent years, with the longer-term vision of Fault-Tolerant Quantum Computation (FTQC) offering significant potential albeit at currently intractable resource costs and quantum error correction (QEC) overheads. For problems of interest, FTQC will require millions of physical qubits with long coherence times, high-fidelity gates, and compact sizes to surpass classical systems. Just as heterogeneous specialization has offered scaling benefits in classical computing, it is likewise gaining interest in FTQC. However, systematic use of heterogeneity in either hardware or software elements of FTQC systems remains a serious challenge due to the vast design space and variable physical constraints.
Noisy Intermediate-Scale Quantum Computing (NISQ) has dominated headlines in recent years, with the longer-term vision of Fault-Tolerant Quantum Computation (FTQC) offering significant potential albeit at currently intractable resource costs and quantum error correction (QEC) overheads. For problems of interest, FTQC will require millions of physical qubits with long coherence times, high-fidelity gates, and compact sizes to surpass classical systems. Just as heterogeneous specialization has offered scaling benefits in classical computing, it is likewise gaining interest in FTQC. However, systematic use of heterogeneity in either hardware or software elements of FTQC systems remains a serious challenge due to the vast design space and variable physical constraints.
Noisy Intermediate-Scale Quantum Computing (NISQ) has dominated headlines in recent years, with the longer-term vision of Fault-Tolerant Quantum Computation (FTQC) offering significant potential albeit at currently intractable resource costs and quantum error correction (QEC) overheads. For problems of interest, FTQC will require millions of physical qubits with long coherence times, high-fidelity gates, and compact sizes to surpass classical systems. Just as heterogeneous specialization has offered scaling benefits in classical computing, it is likewise gaining interest in FTQC. However, systematic use of heterogeneity in either hardware or software elements of FTQC systems remains a serious challenge due to the vast design space and variable physical constraints. This paper meets the challenge of making heterogeneous FTQC design practical by introducing HetArch, a toolbox for designing heterogeneous quantum systems, and using it to explore heterogeneous design scenarios. Using a hierarchical approach, we successively break quantum algorithms into smaller operations (akin to classical application kernels), thus greatly simplifying the design space and resulting tradeoffs. Specializing to superconducting systems, we then design optimized heterogeneous hardware composed of varied superconducting devices, abstracting physical constraints into design rules that enable devices to be assembled into standard cells optimized for specific operations. Finally, we provide a heterogeneous design space exploration framework which reduces the simulation burden by a factor of 10^4 or more and allows us to characterize optimal design points. We use these techniques to design superconducting quantum modules for entanglement distillation, error correction, and code teleportation, reducing error rates by 2.6x, 10.7x, and 3.0x compared to homogeneous systems.
The maturation of quantum computing from theoretical physics to engineering reality presents a complex landscape for stakeholders navigating the transition from Noisy Intermediate-Scale Quantum (NISQ) devices toward Fault-Tolerant Quantum Computation (FTQC). This report provides a comprehensive, technically rigorous analysis of the current quantum ecosystem, examining the hardware mosaic of leading qubit modalities—superconducting circuits, trapped ions, neutral atoms, and silicon spin qubits—and evaluating them against operational metrics, including coherence times, gate fidelities, and cryogenic infrastructure requirements. We dissect the full software stack, differentiating the near-term utility of error mitigation techniques such as Zero-Noise Extrapolation (ZNE) from the long-term necessity of Quantum Error Correction (QEC) and the milestone of logical qubit break-even. The analysis benchmarks hybrid algorithms (VQE, QAOA) and circuit knitting strategies against current cloud-accessible hardware performance, while also addressing the imminent non-computational impact of PostQuantum Cryptography (PQC) migration. Experimental data synthesised from leading vendor roadmaps and pre-print literature indicate that superconducting platforms currently lead in gate speed (nanosecond regime) but face crosstalk scaling challenges beyond 1,000 qubits. In contrast, trapped-ion and neutral-atom architectures demonstrate superior connectivity and coherence. The report concludes with a grounded, evidence-based five-year projection, identifying high-value vertical use cases in pharmaceuticals and finance, and providing a strategic framework for enterprises to separate quantum hype from tangible commercial opportunity. Future research directions include the realisation of low-overhead Quantum LDPC codes and the development of modular photonic interconnects to scale beyond single-chip architectures.
In 2017, John Preskill defined Noisy Intermediate Scale Quantum (NISQ) computers as an intermediate step on the road to large scale error corrected fault-tolerant quantum computers (FTQC). The NISQ regime corresponds to noisy qubit quantum computers with the potential to solve actual problems of some commercial value faster than conventional supercomputers, or consuming less energy. Over five years on, it is a good time to review the situation. While rapid progress is being made with quantum hardware and algorithms, and many recent experimental demonstrations, no one has yet successfully implemented a use case matching the original definition of the NISQ regime. This paper investigates the space, fidelity and time resources of various NISQ algorithms and highlights several contradictions between NISQ requirements and actual as well as future quantum hardware capabilities. It then covers various techniques which could help like qubit fidelities improvements, various breeds of quantum error mitigation methods, analog/digital hybridization, using specific qubit types like multimode photons as well as quantum annealers and analog quantum computers (aka quantum simulators or programmable Hamiltonian simulators) which seem closer to delivering useful applications although they have their own mid to longer-term scalability challenges. Given all the constraints of these various solutions, it seems possible to expect some practical use cases for NISQ systems, but with a very narrow window before various scaling issues show up. Turning to the future, a scenario can be envisioned where NISQ will not necessarily be an intermediate step on the road to FTQC. Instead, the two may develop along different paths, due to their different requirements. This leaves open a key question on the trade-offs that may be necessary to make between qubit scale and qubit fidelities in future quantum computers designs.
The development of fault-tolerant quantum computers (FTQCs) is receiving increasing attention within the quantum computing community. Like conventional digital computers, FTQCs, which utilize error correction and millions of physical qubits, have the potential to address some of humanity’s grand challenges. However, accurate estimates of the tangible scale of future FTQCs, based on transparent assumptions, are uncommon. How many physical qubits are necessary to solve a practical problem intractable for classical hardware? What costs arise from distributing quantum computation across multiple machines? This paper presents an architectural model of a potential FTQC based on superconducting qubits, divided into discrete modules and interconnected via coherent links. We employ a resource-estimation framework and software tool to assess the physical resources required to execute specific quantum algorithms compiled into their graph-state form and arranged onto a modular superconducting hardware architecture. Our tool can predict the size, power consumption, and execution time of these algorithms based on explicit assumptions about the physical layout, thermal load, and modular connectivity of the system. We assess the resources needed for quantum computation examples that serve as building blocks of proposed applications, quantifying the architectural bottlenecks and trade-offs that remain to be addressed to deliver utility.
A universal fault-tolerant quantum computer that can solve efficiently problems such as integer factorization and unstructured database search requires millions of qubits with low error rates and long coherence times. While the experimental advancement towards realizing such devices will potentially take decades of research, noisy intermediate-scale quantum (NISQ) computers already exist. These computers are composed of hundreds of noisy qubits, i.e. qubits that are not error-corrected, and therefore perform imperfect operations in a limited coherence time. In the search for quantum advantage with these devices, algorithms have been proposed for applications in various disciplines spanning physics, machine learning, quantum chemistry and combinatorial optimization. The goal of such algorithms is to leverage the limited available resources to perform classically challenging tasks. In this review, we provide a thorough summary of NISQ computational paradigms and algorithms. We discuss the key structure of these algorithms, their limitations, and advantages. We additionally provide a comprehensive overview of various benchmarking and software tools useful for programming and testing NISQ devices.
Study of the Issue Quantum error correction (QEC) is crucial yet incurs significant qubit overhead costs. The current QEC codes lack sufficient efficiency for near-term devices. The current generation of NISQ devices, which often rely on delicate nanostructured qubit architectures, is prone to noise, decoherence, and gate faults, which severely limit their computing capability and scalability. While traditional quantum error correction codes, such as the surface code, are theoretically resilient, they often require significant qubit overhead and complex management systems that exceed the hardware capabilities of NISQ-era devices. This raises the question of whether new, resource-efficient QEC strategies or hybrid error mitigation approaches can be tailored to the limits of nanostructured NISQ designs. This document examines the constraints of existing quantum error correction (QEC) codes, which are crucial for preserving the fidelity of quantum computations yet require substantial qubit resources. This study examines the shortcomings of current Quantum Error Correction (QEC) codes in relation to Noisy Intermediate-Scale Quantum (NISQ) devices and explores alternative strategies to create more efficient, low-overhead QEC frameworks appropriate for imminent quantum technologies.