Abstract Even though quantum algorithms are designed using an idealised high‐level quantum circuit description, the execution on real devices must consider the backend physical properties. Contemporary noisy intermediate‐scale quantum (NISQ) computers are characterized by limited inter‐qubit connectivity and an exclusive set of native gates, whose execution is affected by non‐negligible errors and non‐idealities. Quantum compilation, consisting of logic and layout synthesis, aims to recast the original circuit description to the target hardware by solving the coupling‐constraint and to minimize the execution time and the error rate. While a previous article addresses the first phase, the second one is the aim of this manuscript. Currently available layout tools mainly target superconducting technology. This article tries to match the unmet need for a layout synthesis library supporting a wider range of technologies. The most promising algorithms already present in the state of the art are adapted to extend the compatibility to all the supported technologies, and new approaches, which exploit the awareness of the coupling strength in fully‐connected topologies, are proposed. The integrated procedures are benchmarked against IBM's Qiskit and Cambridge Quantum Computing's compilation toolchains, and even though these strategies can be further improved, the results are encouraging.
Abstract Even though quantum algorithms are designed using an idealised high‐level quantum circuit description, the execution on real devices must consider the backend physical properties. Contemporary noisy intermediate‐scale quantum (NISQ) computers are characterized by limited inter‐qubit connectivity and an exclusive set of native gates, whose execution is affected by non‐negligible errors and non‐idealities. Quantum compilation, consisting of logic and layout synthesis, aims to recast the original circuit description to the target hardware by solving the coupling‐constraint and to minimize the execution time and the error rate. While a previous article addresses the first phase, the second one is the aim of this manuscript. Currently available layout tools mainly target superconducting technology. This article tries to match the unmet need for a layout synthesis library supporting a wider range of technologies. The most promising algorithms already present in the state of the art are adapted to extend the compatibility to all the supported technologies, and new approaches, which exploit the awareness of the coupling strength in fully‐connected topologies, are proposed. The integrated procedures are benchmarked against IBM's Qiskit and Cambridge Quantum Computing's compilation toolchains, and even though these strategies can be further improved, the results are encouraging.
Abstract With noisy intermediate scale quantum computers (NISQ) becoming larger in scale and more reliable, quantum circuits are growing in size and complexity. In order to face the challenge of achieving optimal circuits, design automation approaches for improving and mapping quantum circuits on different architectures have been proposed, each one characterized by a specific optimization strategy. In this article, the use of a template-based approach for quantum circuits optimization purposes is explored, and the proposal of a modular compilation toolchain, which supports three quantum technologies (nuclear magnetic resonance, trapped ions and superconducting qubits), is presented. The toolchain tackles the task of implementing logic synthesis for single-qubit and multi-qubit gates in the compilation process and it is structured with multiple steps and modular libraries. The toolchain was tested through a benchmarking procedure, and the results for a subset of complex quantum circuits as inputs are here reported, alongside a comparison with those provided by the compilers of IBM’s Qiskit and Cambridge Quantum Computing’s t∣ket⟩ t|ket . The current toolchain prototype was crafted to be an easily expandable and reliable core for future developments, which could lead it to support even more quantum technologies and a fully fledged layout synthesis. Nonetheless, the obtained results are quite encouraging, and they prove that in certain conditions the Toolchain can be competitive in quantum circuits optimization, especially when dealing with single-qubit gates.
In recent years, the emergence of the Noisy Intermediate-Scale Quantum (NISQ) era has led to the development of a wide variety of quantum devices, marking a dynamic phase in the field of quantum computing. Despite these advancements, practical applications of quantum computers still face significant challenges, one of the most prominent being the limited connectivity between physical quantum bits (qubits). This limitation requires quantum circuits to be recompiled through layout synthesis before they can be executed on quantum devices. Layout synthesis determines the specific placement of quantum gates within the circuit on the physical hardware. When gates do not align with the connectivity constraints of the device, additional quantum gates must be inserted to remap the qubits, which can negatively affect the circuit’s efficiency and performance. To address this issue, the primary goal of this paper is to enhance the mapping process within layout synthesis, aiming to optimize both the layout and the circuit depth. Experimental results demonstrate that the proposed method effectively reduces the quantum circuit depth, outperforming other existing approaches in terms of efficiency.
The rapid evolution of Noisy Intermediate-Scale Quantum (NISQ) devices has intensified the need for robust compilation strategies capable of mitigating hardware-induced errors while maximizing computational efficiency. Quantum compilers play a pivotal role in translating high-level quantum algorithms into hardware-executable instructions, yet they face significant challenges related to qubit connectivity constraints, limited coherence times, and stochastic noise. This paper examines error-resilient quantum compiler design for efficient qubit mapping, gate optimization, and noise mitigation in NISQ-era devices, proposing a framework that integrates topology-aware mapping, adaptive gate synthesis, and probabilistic error suppression techniques. By synthesizing advances in quantum circuit optimization, hardware-aware scheduling, and hybrid classical–quantum error correction strategies, the study evaluates how compiler-level innovations can substantially enhance execution fidelity and resource efficiency. The findings suggest that intelligent compiler architectures are critical enablers of practical quantum advantage during the transitional NISQ phase, bridging theoretical algorithm design with real-world hardware constraints.
We present an algorithm for compiling arbitrary unitaries into a sequence of gates native to a quantum processor. As CNOT gates are error-prone for the foreseeable Noisy-Intermediate-Scale Quantum devices era, our A* inspired algorithm minimizes their count while accounting for connectivity. We discuss the formulation of synthesis as a search problem as well as an algorithm to find solutions. For a workload of circuits with complexity appropriate for the NISQ era, we produce solutions well within the best upper bounds published in literature and match or exceed hand tuned implementations, as well as other existing synthesis alternatives. In particular, when comparing against state-of-the-art available synthesis packages we show 2.4× average (up to 5.3×) reduction in CNOT count. We also show how to re-target the algorithm for a different chip topology and native gate set while obtaining similar quality results. We believe that tools like ours can facilitate algorithmic exploration and guide gate set discovery for quantum processor designers, as well as being useful for optimization in the quantum compilation tool-chain.
The rapid advancement of Noisy Intermediate-Scale Quantum (NISQ) devices has driven the need for efficient design automation tools that can translate complex engineering models into executable quantum circuits. This study explores the development of automated quantum circuit design frameworks focused on gate optimization and noise-aware compilation, enabling practical quantum computation for engineering applications such as optimization, simulation, and control systems. Traditional circuit design methods often fail to account for hardware constraints, decoherence, and gate infidelity, which significantly affect computational accuracy on NISQ devices. To address these challenges, this research introduces a hybrid automation approach combining quantum transpilation, variational circuit pruning, and error-aware synthesis algorithms to enhance circuit reliability and scalability. The framework integrates quantum-classical co-design principles to optimize both logical and physical circuit layers, leveraging hardware-specific calibration data to adapt compilation strategies dynamically. Through simulations and benchmark analysis, the proposed system demonstrates significant improvements in quantum resource utilization, error mitigation, and gate depth reduction compared to conventional compilation methods. This work underscores the growing importance of design automation in quantum engineering, where algorithmic efficiency must be harmonized with physical constraints to realize functional and scalable quantum workflows. By establishing a methodology for gate-level optimization and noise-adaptive design, the study contributes to bridging the gap between theoretical quantum algorithms and real-world engineering implementations within the NISQ computing era.
Abstract With the development in the field of quantum physics, several methods for building a quantum computer have emerged. These differ in qubit technologies, interaction topologies, and noise characteristics. In this article, insights are given into the circuit‐centric architecture design of Noisy Intermediate‐Scale Quantum (NISQ) devices. The dependence of the circuit size, circuit depth on the interaction and connection between different qubits present in quantum hardware are discussed. A noise‐aware procedure is presented which helps in determining the optimal interactions between different qubits of a quantum chip to execute a given circuit in the most efficient way possible. In this article, the 5‐qubit hardware in a noiseless setting is illustrated with an example. Also, a benchmark‐driven analysis is performed to show the importance of noise adaptivity in determining the hardware reliability. It is concluded that a generalized and flexible procedure such as this approach can aid in determining the design of hardware accurately for which the circuit runs efficiently, that is, with the least number of clock cycles, the lowest gate operations, and noise‐based errors.