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International Conference on Natural Computation, Fuzzy Systems and Knowledge Discovery (ICNC-FSKD)

Design of F-L-QC-LDPC Decoder Based on LNMS Decoding Algorithm

Youyao Liu, Haimei Huang, Jialei Gao, Shihao Gai

Published Jul 29, 2023• 1 citation
Publisher

Abstract

Low Density Parity Check Code (LDPC) can meet the decoding requirements of a variety of code lengths and rates in different communication scenarios, but the LDPC code check matrix is irregular, which has problems with difficult storage and reading of the check matrix and high coding complexity. For the decoding requirements of multi-code length, this paper proposes a Quasi Crystal Low Density Parity Check Codes (QCLDPC) code based on Fibonacci Lucas sequence, which can obtain the codewords with different code length and code rate by changing the number of rows and columns of the exponential matrix. In terms of decoding algorithms, the Layered Non-Maximum Suppression (LNMS) decoding algorithm, which combines the minimum sum decoding algorithm with the layered algorithm, is proposed to improve the convergence speed of decoding iteration and decoder throughput. Through simulation and comparative experiments, it is proved that this design can support a variety of bit rates, block lengths and sub matrix sizes, and meet the requirements of high throughput and low complexity decoder in modern communication systems.

DOI
10.1109/icnc-fskd59587.2023.10280802

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Low Density Parity Check Code (LDPC) can meet the decoding requirements of a variety of code lengths and rates in different communication scenarios, but the LDPC code check matrix is irregular, which has problems with difficult storage and reading of the check matrix and high coding complexity. For the decoding requirements of multi-code length, this paper proposes a Quasi Crystal Low Density Parity Check Codes (QCLDPC) code based on Fibonacci Lucas sequence, which can obtain the codewords with different code length and code rate by changing the number of rows and columns of the exponential matrix. In terms of decoding algorithms, the Layered Non-Maximum Suppression (LNMS) decoding algorithm, which combines the minimum sum decoding algorithm with the layered algorithm, is proposed to improve the convergence speed of decoding iteration and decoder throughput. Through simulation and comparative experiments, it is proved that this design can support a variety of bit rates, block lengths and sub matrix sizes, and meet the requirements of high throughput and low complexity decoder in modern communication systems.
Entering the 5G era, the hardware design of low-density parity-check (LDPC) codes under the new standard has increasingly higher requirements on throughput. According to the geometric characteristics of the check matrices of the quasi-cyclicQC) LDCP codes under the CCSDS standard, this paper designs a layered dynamic normalized minimum sum algorithm(LDNMSA) under the pre-termination decoding based on de-layering scheme. The check matrix structure of this code is easy for hardware design and the storage resource consumption is low. The approximate replacement of the minimum sum algorithm(MSA) reduces the computational complexity of the check node update process. The determination of correction factors and inter-layer deletion thresholds through computer simulation improves the decoding performance and the speed of a single iteration, and adopt the layered scheduling scheme with optimized update order reduces the number of iterations required for decoding. Experimental results show that when the bit error rate(BER) is 10-5, the designed algorithm has a gain of approximately 0.5 dB compared to the MSA. The speed and calculation amounts to a single iteration are much lower than the log-likelihood-ratio(LLR) belief propagation(BP) algorithm and the performance is only less than 0.1dB.
To address the low throughput and high storage resource consumption of the low density parity-check decoder,this paper proposes a layered decoding algorithm of QC-LDPC codes.The algorithm uses the receiving channel module to initialize the likelihood ratio information.Then the storage check information and posteriori information are combined to generate a node self-updating decoding algorithm based on the layered minimum sum.The decoder is judged based on the sign bit of posterior information.Simulation results show that the storage resources of the improved decoder are saved by 20% compared with the traditional decoder.When the number of iterations is 10,the throughput can reach 516.8 Mb/s.
Quasi-cyclic low-density parity-check (QC-LDPC) codes are linear block codes with performance close to the Shannon limit. The layered minimum sum (LMS) decoding algorithm speeds up the decoding convergence by layering the check matrix and updating the nodes according to the layers. However, the MS algorithm has the problem of over estimation and affects the decoding performance due to its simplified strategy of MS algorithm updating the message of check nodes. Therefore, this paper proposes a layered minimum sum decoding algorithm based on overestimation. By setting the correction threshold and updating the check nodes by the conditions, the decoding performance is improved. When the code length is 2048 and the bit error rate is , the proposed algorithm can improve the decoding convergence speed by about 25% and obtain a coding gain of about 0.1 dB.
Forward error correcting codes are successfully implemented in high speed communication for error-free transmission with high data rate. One such code is Low Density Parity Check (LDPC) code. In this paper, Quasi Cyclic (QC) construction of LDPC code is used and we investigate the performance of various decoding algorithms of QC-LDPC code. Their performances in terms of error correction and complexity are compared. The speed of convergence of various decoding algorithms of LDPC code is analyzed by using the Density Evolution theory. With this thresholding in iterations, the BER performances of different algorithms are simulated. Our results show that the same BER performance can be achieved with reduced number of iterations or the speed of the system can be improved without much sacrifice in BER performance.
In this paper, a combined Low-Density Parity-Check (LDPC) code decoding design method, called modified Block-Type LDPC (B-LDPC), for realistic LDPC coding system architectures is presented. The B-LDPC code, which is a special class of quasi-cyclic LDPC (QC-LDPC), has an efficient encoding algorithm owing to the simple structure of their parity-check matrices. A proposed distribution of irregular parity-check matrix for the modified B-LDPC is developed so that we can obtain an area-efficient decoder design, good error correction performance, and achievable architecture implementation. The modified B-LDPC code decoding utilizes the iterative min-sum algorithm (MSA) and its decoding architecture design employs the non-overlapping operations of bit node unit (BNU) and check node unit (CNU). Different block matrix sizes for parity-check matrix can be adopted so that the modified B-LDPC code decoding improves the throughput without obvious performance degradation.
The recently proposed single block-row quasi-cyclic low-density parity-check (QC-LDPC) codes are favorable for high-speed applications. However, conventional decoder design methods are not suitable for this kind of codes. To tackle this issue, this paper aims at designing efficient column-layered single block-row QC-LDPC decoder architecture without affecting the decoding performance. Moreover, the simplified version which only requires single minimum value is also proposed for further hardware reduction. Results show that, for the rate-0.9006 (1640, 1477) single block-row QC-LDPC code, the proposed two designs achieves significant advantages in both hardware and latency over their row-layered counterpart.