Invertible logic can realize bidirectional operations of a function represented by a Hamiltonian (energy) with noise and can be applied for integer factorization and training neural networks. However, the computation error is not negligible due to becoming trapped at the local minimum energy when the Hamiltonian is large. This paper introduces self-adaptive gate control (SAGC) for high convergence rates to the global minimum energy on invertible logic. From our analysis based on simulating small-scale invertible logic circuits, it is supposed that becoming stuck is caused by invalid states of invertible gates. The proposed SAGC autonomously detects invalid gates by checking the truth tables and adds large noise to them for efficient escape from the local minimum energy. As a typical example of invertible logic, invertible adders, multipliers and multiplexers are designed and evaluated. The simulation results show that the convergence probabilities to the global minimum based on SAGC are a few times higher than those based on a conventional method that equally adds noise to all the gates.
Invertible logic can realize bidirectional operations of a function represented by a Hamiltonian (energy) with noise and can be applied for integer factorization and training neural networks. However, the computation error is not negligible due to becoming trapped at the local minimum energy when the Hamiltonian is large. This paper introduces self-adaptive gate control (SAGC) for high convergence rates to the global minimum energy on invertible logic. From our analysis based on simulating small-scale invertible logic circuits, it is supposed that becoming stuck is caused by invalid states of invertible gates. The proposed SAGC autonomously detects invalid gates by checking the truth tables and adds large noise to them for efficient escape from the local minimum energy. As a typical example of invertible logic, invertible adders, multipliers and multiplexers are designed and evaluated. The simulation results show that the convergence probabilities to the global minimum based on SAGC are a few times higher than those based on a conventional method that equally adds noise to all the gates.
Adaptive quantum computing control is important for the stability and efficiency of quantum systems, especially in the presence of dynamic environmental noise and hardware fluctuations. We present a unified strategy for machine learning (ML) techniques to improve adaptive quantum control in two main directions: optimization speed and out-of-sample error. Here, we propose a hybrid learning method combining reinforcement learning (RL), deep neural networks (DNNs), and quantum-inspired models to actively and adaptively update quantum gate parameters and error mitigation strategies on the fly. Embedding of quantum noise models directly into the learning allows the system to predict and correct for decoherence, gate errors and measurement inaccuracy before they affect computational fidelity. Using extensive simulations as well as experimental validation on noisy intermediate-scale quantum (NISQ) processors, our improved ML model achieves a substantially higher fidelity and robustness compared to standard model-free and static control approaches. We introduce a novel feedback-loop mechanism based on online learning algorithms enabling the system to adjust for changing noise profiles and hardware drift without retraining. The optimization part uses metaheuristic methods to quickly converge to control parameters that perform well, and the error prevention mechanism features anomaly detection and prediction correction layers to minimize the effects of cumulative decoherence. The results demonstrate that our adaptive control framework can be used to not only speed up the convergence in training quantum algorithms, but also sustain the performance of gates against error at a variety of error rates with the reduction of the real-time impact of the error up to 35 %. This work highlights the promise of machine learningaugmented quantum control for improving reliability and scalability in quantum computing and serves as a stepping stone for future incorporation with fault-tolerant designs.
Noisy Intermediate-Scale Quantum (NISQ) devices are promising platforms for practical quantum computing, but their performance is significantly affected by limited qubit availability, gate errors, decoherence, circuit depth, and hardware-dependent noise. Conventional quantum circuits are generally designed and optimized before execution and may not respond effectively to changing hardware conditions during computation. This research proposes a Self-Adaptive Quantum Circuit framework that dynamically modifies quantum circuits according to the current computational resources and noise characteristics of NISQ devices. The proposed framework monitors parameters such as qubit fidelity, gate error rates, circuit depth, execution time, and resource availability, and automatically selects suitable circuit configurations to improve computational performance. Adaptive mechanisms can be employed to reduce unnecessary gates, optimize qubit utilization, and mitigate the impact of hardware noise while maintaining the required computational accuracy. The framework will be evaluated using simulation platforms and available NISQ quantum hardware, comparing adaptive circuits with conventional static circuits using metrics such as accuracy, fidelity, circuit depth, gate count, execution time, and error rate. The expected outcome is a resource-efficient and noise-aware quantum circuit optimization approach capable of improving the reliability and performance of quantum applications on near-term quantum hardware. The proposed research aims to contribute toward more practical, flexible, and hardware-aware quantum computing systems for NISQ-era applications. Keywords: NISQ Computing, Self-Adaptive Quantum Circuits, Quantum Circuit Optimization, Quantum Error Mitigation, Quantum Noise, Quantum Computing.
Invertible logic has been recently presented that can realize bidirectional computing based on Hamiltonians for solving several critical issues, such as integer factorization and training neural networks. However, a hardware architecture for supporting large-scale general-purpose invertible logic has not been studied. In this paper, we introduce a scalable hardware architecture based on sparse Hamiltonian matrices. In order to store and compute the Hamiltonians efficiently in hardware, a sparse matrix representation of PTELL (partitioned and transposed ELLPACK) is proposed. A memory size of PTELL can be smaller than that of a conventional ELL by reducing the number of paddings while parallel reading of non-zero values are realized for high-throughput operations. As a result, PTELL achieves around 1% and 10% memory usages of a conventional dense and ELL matrices, respectively, in case of invertible multipliers. In addition, the proposed hardware accelerator of invertible logic for supporting arbitrary Hamiltonians is implemented on Xilinx VU9P FPGA, which achieves around two orders of magnitude faster than a 16-core Intel Xeon implementation.
Quantum computing represents a paradigm shift in computation by leveraging the principles of quantum mechanics such as superposition, entanglement, and interference to perform operations beyond classical limitations. Unlike classical computing systems that rely on irreversible logic operations and suffer from energy dissipation due to information loss, quantum systems utilize reversible unitary transformations that preserve information and improve computational efficiency. This paper presents a comprehensive framework for the design, simulation, and validation of quantum gates and reversible arithmetic circuits, including half adders and half subtractors. The proposed approach systematically maps classical arithmetic logic into quantum circuits using fundamental quantum gates such as Pauli-X, Hadamard, Controlled-NOT (CNOT), and Toffoli gates. The circuits are implemented and simulated using the Qiskit Aer framework, enabling detailed analysis of quantum state evolution and measurement outputs. The results obtained from simulation include program-level outputs, state vector representations, measurement counts, and probability distributions, all of which demonstrate strong agreement with classical truth tables. The analysis confirms the correctness, reversibility, and scalability of the proposed designs. Furthermore, a comparative performance evaluation highlights the advantages of quantum computing over classical approaches in terms of parallelism and energy efficiency. The proposed framework establishes a robust foundation for future implementation of complex Boolean logic and arithmetic operations in quantum systems.
This paper explores the design and implementation of self-correcting quantum circuits, a paradigm shift from traditional passive error correction strategies in quantum computing. The core concept involves creating quantum circuits capable of autonomously detecting and rectifying errors through adaptive control mechanisms. This is achieved by utilizing ancillary qubits for real-time monitoring of circuit dynamics and employing a reinforcement learning (RL) agent to dynamically adjust control pulses, thereby minimizing decoherence and maximizing quantum fidelity. The proposed approach moves beyond passive correction, introducing an active system that responds intelligently to errors as they occur. The theoretical framework and the underlying mechanisms are detailed, laying the groundwork for future research and development in robust and resilient quantum computation. The key advancements lie in the integration of dynamic monitoring and adaptive control, offering a potentially significant step towards fault-tolerant quantum computing.
Digital circuits, the backbone of modern computation, are increasingly vulnerable to errors arising from environmental noise, including electromagnetic interference, thermal fluctuations, and process variations. These errors can propagate through circuits, leading to unreliable operation and potentially catastrophic failures, particularly in critical applications like aerospace, defense, and high-performance computing. This paper proposes a novel approach to mitigating these errors by leveraging the principles of Quantum Annealing (QA) to create self-correcting digital circuits. The core concept involves dynamically optimizing the circuit's design and operational parameters in real-time, responding to detected noise and implementing corrective actions. We formulate the circuit self-correction problem as an optimization problem amenable to QA. The objective function incorporates error detection metrics and the desired circuit performance. The QA algorithm iteratively explores the design space, identifying configurations that minimize the impact of noise and achieve the target functionality. Mathematical formulations detail the error modeling, the optimization problem, and the QA algorithm's core steps. The proposed method offers a fundamentally new approach to circuit design and operation, potentially leading to significantly more robust and reliable digital systems.