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IEEE Open Journal of Circuits and Systems

Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices

Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu

Published Jan 1, 2021• 6 citations
Publisher

Abstract

Invertible logic has been recently presented that can realize bidirectional computing based on Hamiltonians for solving several critical issues, such as integer factorization and training neural networks. However, a hardware architecture for supporting large-scale general-purpose invertible logic has not been studied. In this paper, we introduce a scalable hardware architecture based on sparse Hamiltonian matrices. In order to store and compute the Hamiltonians efficiently in hardware, a sparse matrix representation of PTELL (partitioned and transposed ELLPACK) is proposed. A memory size of PTELL can be smaller than that of a conventional ELL by reducing the number of paddings while parallel reading of non-zero values are realized for high-throughput operations. As a result, PTELL achieves around 1% and 10% memory usages of a conventional dense and ELL matrices, respectively, in case of invertible multipliers. In addition, the proposed hardware accelerator of invertible logic for supporting arbitrary Hamiltonians is implemented on Xilinx VU9P FPGA, which achieves around two orders of magnitude faster than a 16-core Intel Xeon implementation.

DOI
10.1109/ojcas.2021.3116584

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Invertible logic has been recently presented that can realize bidirectional computing based on Hamiltonians for solving several critical issues, such as integer factorization and training neural networks. However, a hardware architecture for supporting large-scale general-purpose invertible logic has not been studied. In this paper, we introduce a scalable hardware architecture based on sparse Hamiltonian matrices. In order to store and compute the Hamiltonians efficiently in hardware, a sparse matrix representation of PTELL (partitioned and transposed ELLPACK) is proposed. A memory size of PTELL can be smaller than that of a conventional ELL by reducing the number of paddings while parallel reading of non-zero values are realized for high-throughput operations. As a result, PTELL achieves around 1% and 10% memory usages of a conventional dense and ELL matrices, respectively, in case of invertible multipliers. In addition, the proposed hardware accelerator of invertible logic for supporting arbitrary Hamiltonians is implemented on Xilinx VU9P FPGA, which achieves around two orders of magnitude faster than a 16-core Intel Xeon implementation.
We introduce a scalable hardware architecture for large-scale invertible logic. Invertible logic has been recently presented that can realize bidirectional computing probabilis-tically based on Hamiltonians with a small number of non-zero elements. In order to store and compute the Hamiltonians efficiently in hardware, a sparse matrix representation of PTELL (partitioned and transposed ELLPACK) is proposed. A memory size of PTELL can be smaller than that of a conventional ELL by reducing the number of paddings while parallel reading of non-zero values are realized for high-throughput operations. As a result, the proposed scalable invertible-logic hardware based on PTELL is designed on Xilinx KC705 FPGA board, which achieves two orders of magnitude faster than an 8-core CPU implementation.
In recent years, hardware implementations of Ising machines have emerged as a viable alternative to quantum computing for solving hard optimization problems among other applications. Unlike quantum hardware, dense connectivity can be achieved in classical systems. However, we show that dense connectivity leads to severe frequency slowdowns and interconnect congestion scaling unfavorably with system sizes. As a scalable solution, we propose a systematic sparsification method for dense graphs by introducing copy nodes to limit the number of neighbors per graph node. In addition to solving interconnect congestion, this approach enables constant frequency scaling where all spins in a network can be updated in constant time. On the other hand, sparsification introduces new difficulties, such as constraint-breaking between copied spins and increased convergence times to solve optimization problems, especially if exact ground states are sought. Relaxing the exact solution requirements, we find that the overheads in convergence times are milder. We demonstrate these ideas by designing probabilistic bit Ising machines using ASAP7 (a predictive 7nm FinFET technology model) process design kits as well as Field Programmable Gate Array (FPGA)-based implementations. Finally, we show how formulating problems in naturally sparse networks (e.g., by invertible logic) sidesteps challenges introduced by sparsification methods. Our results are applicable to a broad family of Ising machines using different hardware implementations.
Quantum emulators play an important role in the development and testing of quantum algorithms, especially given the limitations of the current FTQC era. Developing high-speed, memory-optimized quantum emulators is a growing research trend, with gate fusion being a promising technique. However, existing gate fusion implementations often struggle to efficiently support large-scale quantum systems with a high number of qubits due to a lack of optimizations for the exponential growth in memory requirements. Therefore, this study proposes the MEMS (Memory-Efficient Matrix Storage) method for storing quantum operators and states, along with a MEMS-based Quantum Emulator Accelerator (QEA) architecture that incorporates multiple processing elements (PEs) to accelerate tensor product and matrix multiplication computations in quantum emulation with gate fusion. The theoretical analysis of the QEA on the Xilinx ZCU102 FPGA, using varying numbers of PEs and different depths of unitary and local data memory, reveals a linear increase in memory depth with the number of qubits. This scaling highlights the potential of the MEMS-based QEA to accommodate larger quantum circuits, providing insights into selecting appropriate memory sizes and FPGA devices. Furthermore, the estimated performance of the QEA with PE counts ranging from 22to 25on the Xilinx ZCU102 FPGA demonstrates that increasing the number of PEs significantly reduces the computation cycle count for circuits with fewer than 18 qubits, making it substantially faster than previous works.
The core step in quantum simulations is typically matrix vector multiplication $φ= \Hmat ψ$. Executing this step is limited by memory requirement to store the Hamiltonian. We present a memory-scalable, hardware-adaptive matrix-free framework for applying large operators on vectors without materializing the full matrix on a single accelerator. The operator is represented through a block-procedural interface: blocks may be generated, loaded, cached, distributed, or applied directly only when their action is needed. For quantum simulation, it provides the core kernel for quantum operations. An adaptive planner selects block size, cache strategy, GPU grouping, row distribution, and task parallelization from memory and workload estimates. We describe analytic, measured, and learned planning strategies that choose between procedural generation, partial caching, full caching, and row-distributed caching. The method removes the requirement that the full dense matrix fit in the accelerator memory. This shifts large simulations from a fixed memory barrier to a tunable balance between block generation, cache reuse, data movement, parallel scheduling, and numerical accuracy.
Quantum emulators play an important role in the development and testing of quantum algorithms, especially given the limitations of the current FTQC era. Developing high-speed, memory-optimized quantum emulators is a growing research trend, with gate fusion being a promising technique. However, existing gate fusion implementations often struggle to efficiently support large-scale quantum systems with a high number of qubits due to a lack of optimizations for the exponential growth in memory requirements. Therefore, this study proposes the EMMS (Efficient-Memory Matrix Storage) method for storing quantum operators and states, along with an EMMS-based Quantum Emulator Accelerator (QEA) architecture that incorporates multiple processing elements (PEs) to accelerate tensor product and matrix multiplication computations in quantum emulation with gate fusion. The theoretical analysis of the QEA on the Xilinx ZCU102 FPGA, using varying numbers of PEs and different depths of unitary and local data memory, reveals a linear increase in memory depth with the number of qubits. This scaling highlights the potential of the EMMS-based QEA to accommodate larger quantum circuits, providing insights into selecting appropriate memory sizes and FPGA devices. Furthermore, the estimated performance of the QEA with PE counts ranging from 222^222 to 252^525 on the Xilinx ZCU102 FPGA demonstrates that increasing the number of PEs significantly reduces the computation cycle count for circuits with fewer than 18 qubits, making it significantly faster than previous works.
Current approaches for emulation of quantum algorithms on classical parallel hardware like FPGA suffer with three main issues: exponential usage of logic elements, synthesis takes exponential time and difficulty of implementation. In this paper we propose a processor architecture capable of efficiently emulate quantum circuits, reducing the mishaps of previous similar proposals. We compare our results to previous works with respect to a common benchmark and validate the architecture using FPGA. Our approach has better scalability in logic cell usage, a better management of the need of re-synthesis and easier implementation.