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SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems

Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices

Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu

Published Oct 1, 2021• 2 citations
Publisher

Abstract

We introduce a scalable hardware architecture for large-scale invertible logic. Invertible logic has been recently presented that can realize bidirectional computing probabilis-tically based on Hamiltonians with a small number of non-zero elements. In order to store and compute the Hamiltonians efficiently in hardware, a sparse matrix representation of PTELL (partitioned and transposed ELLPACK) is proposed. A memory size of PTELL can be smaller than that of a conventional ELL by reducing the number of paddings while parallel reading of non-zero values are realized for high-throughput operations. As a result, the proposed scalable invertible-logic hardware based on PTELL is designed on Xilinx KC705 FPGA board, which achieves two orders of magnitude faster than an 8-core CPU implementation.

DOI
10.1109/sips52927.2021.00047

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We introduce a scalable hardware architecture for large-scale invertible logic. Invertible logic has been recently presented that can realize bidirectional computing probabilis-tically based on Hamiltonians with a small number of non-zero elements. In order to store and compute the Hamiltonians efficiently in hardware, a sparse matrix representation of PTELL (partitioned and transposed ELLPACK) is proposed. A memory size of PTELL can be smaller than that of a conventional ELL by reducing the number of paddings while parallel reading of non-zero values are realized for high-throughput operations. As a result, the proposed scalable invertible-logic hardware based on PTELL is designed on Xilinx KC705 FPGA board, which achieves two orders of magnitude faster than an 8-core CPU implementation.
Invertible logic has been recently presented that can realize bidirectional computing based on Hamiltonians for solving several critical issues, such as integer factorization and training neural networks. However, a hardware architecture for supporting large-scale general-purpose invertible logic has not been studied. In this paper, we introduce a scalable hardware architecture based on sparse Hamiltonian matrices. In order to store and compute the Hamiltonians efficiently in hardware, a sparse matrix representation of PTELL (partitioned and transposed ELLPACK) is proposed. A memory size of PTELL can be smaller than that of a conventional ELL by reducing the number of paddings while parallel reading of non-zero values are realized for high-throughput operations. As a result, PTELL achieves around 1% and 10% memory usages of a conventional dense and ELL matrices, respectively, in case of invertible multipliers. In addition, the proposed hardware accelerator of invertible logic for supporting arbitrary Hamiltonians is implemented on Xilinx VU9P FPGA, which achieves around two orders of magnitude faster than a 16-core Intel Xeon implementation.
In recent years, hardware implementations of Ising machines have emerged as a viable alternative to quantum computing for solving hard optimization problems among other applications. Unlike quantum hardware, dense connectivity can be achieved in classical systems. However, we show that dense connectivity leads to severe frequency slowdowns and interconnect congestion scaling unfavorably with system sizes. As a scalable solution, we propose a systematic sparsification method for dense graphs by introducing copy nodes to limit the number of neighbors per graph node. In addition to solving interconnect congestion, this approach enables constant frequency scaling where all spins in a network can be updated in constant time. On the other hand, sparsification introduces new difficulties, such as constraint-breaking between copied spins and increased convergence times to solve optimization problems, especially if exact ground states are sought. Relaxing the exact solution requirements, we find that the overheads in convergence times are milder. We demonstrate these ideas by designing probabilistic bit Ising machines using ASAP7 (a predictive 7nm FinFET technology model) process design kits as well as Field Programmable Gate Array (FPGA)-based implementations. Finally, we show how formulating problems in naturally sparse networks (e.g., by invertible logic) sidesteps challenges introduced by sparsification methods. Our results are applicable to a broad family of Ising machines using different hardware implementations.
Scaling qubit control is a key issue for Large Scale Quantum (LSQ) computing and hardware control systems are increasingly costly in logic and memory resources. We present a newly developed compact Direct Digital Synthesis (DDS) architecture for signal generation for spin qubits that is scalable in terms of waveform accuracy and the number of synchronized channels. Fine control of gate voltages is achieved by on-the-fly generation of very precise ramps. Embedded memory requirements are reduced by orders of magnitude compared to current Arbitrary Waveform Generator (AWG) architectures, removing a major scalability barrier for quantum computing.
The quantum computer is emerging technology since it can resolve complex tasks such as factorization or search problem faster than classical computers. However, simulation of the quantum computer is difficult because computational load increases exponentially as the number of qubits used in the circuit is increased. This paper proposes a hardware architecture for quantum circuit simulation. To implement simulator smaller, our architecture operates based on a 1-input single gate regardless of the number of qubits used in the circuit In addition, our architecture helps to reduce simulation time by skipping calculation and data transfer. The proposed architecture is implemented on FPGA and the experimental results show that our architecture reduces 79.2% of the multiplication process when we simulate 20-qubit quantum Fourier transform with a small hardware size.
Current approaches for emulation of quantum algorithms on classical parallel hardware like FPGA suffer with three main issues: exponential usage of logic elements, synthesis takes exponential time and difficulty of implementation. In this paper we propose a processor architecture capable of efficiently emulate quantum circuits, reducing the mishaps of previous similar proposals. We compare our results to previous works with respect to a common benchmark and validate the architecture using FPGA. Our approach has better scalability in logic cell usage, a better management of the need of re-synthesis and easier implementation.
Reversible computing has emerged as a promising solution for reducing energy dissipation in digital systems by addressing the fundamental limitations caused by information loss.Quaternary reversible logic, which uses multi-valued representations, provides higher information density, reduced interconnect complexity, and better scalability when compared to conventional binary logic.This work presents the design and implementation of a quaternary reversible Arithmetic Logic Unit (ALU) that integrates essential computational modules, including arithmetic units, logical units, memory units, decoders, and multiplexers.The proposed architecture supports efficient data routing and precise operation control through a scalable control unit and a selection-line-based design approach.The designed ALU demonstrates reduced quantum cost, fewer garbage outputs, and minimized constant inputs in comparison with existing reversible ALU designs, while remaining compatible with larger reversible and quantum computing architectures.Simulation results and comparative analysis validate the improved efficiency and low-power potential of the proposed system, making it suitable for next-generation computing applications.The complete design is implemented using Verilog HDL and synthesized and simulated using Xilinx Vivado Design Suite 2025.