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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

Concise Memory Organization for a Customizable Hardware Design of a Quantum Coprocessor

Nadia Nedjah, Sérgio Raposo, Luiza de Macedo Mourelle

Published Feb 27, 2023• 3 citations
Publisher

Abstract

This work proposes a concise memory organization for an efficient customizable hardware design of a coprocessor that is able to perform quantum computations, exploring pure parallelism as well as a pipelined execution. The architecture is based on a quantum state memory, an operator memory, and a scratch memory, besides the calculation unit, the measurement unit and the control unit. All functional units communicate with each other via dedicated and shared data buses, depending information exchange frequency. In this paper, we focus on memory organization.

DOI
10.1109/lascas56464.2023.10108201

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This work proposes a concise memory organization for an efficient customizable hardware design of a coprocessor that is able to perform quantum computations, exploring pure parallelism as well as a pipelined execution. The architecture is based on a quantum state memory, an operator memory, and a scratch memory, besides the calculation unit, the measurement unit and the control unit. All functional units communicate with each other via dedicated and shared data buses, depending information exchange frequency. In this paper, we focus on memory organization.
This work proposes a customizable hardware design of a coprocessor that is able to perform quantum computations, exploring pure parallelism as well as a pipelined execution. The architecture is based on a quantum state memory, a scratch memory, a calculation unit, a measurement unit and, a control unit. All functional units communicate with each other via dedicated and shared data buses, depending information exchange frequency. The design is simulated and proven to be effective in executing quantum operations.
This chapter discusses the overall hardware architecture of a quantum processor. Emulation of quantum processing requires primarily an efficient way to store and retrieve quantum information. The quantum processor employs different purpose memories. The proposed co-processor implements a quantum machine capable of performing certain quantum operations on a set of q-bits that form the machine quantum state. It is an isolated system that interacts with a host processor through communication channels. The main processor sends properly formatted commands that invoke quantum operations on q-bits, to manipulate the quantum state. The channel configuration is used because it considers the sequential characteristic of a quantum algorithm due to the potential dependence of the result of the previous operation on one or more q-bits. The full-duplex configuration would also be possible, given the required control related to data dependency. The interaction between the units and memories that compose the co-processor is done via data buses, address buses and/or control buses.
It is shown that true quantum computers are analog and probabilistic computers and, in fact,they play the role of coprocessors in relation to classical computers. A digital quantum coprocessor consists of digital qubits. Each digital qubit is a finite state machine, the state changes of which is described in the same way as the state changes of an analog qubit. A digital qubit is a chain of digital quantum gates. Each digital quantum gate is digital unit, the state changes of which is described in the same way as the state changes of an analog quantum gate. The main difference between digital qubit and digital quantum gate from analog ones is the presence of memory (more precisely, the possibility of its introduction into their circuit) and its use for organizing calculations. A digital qubit without feedbacks - a digital quantum gate that can be controlled using a classic computer, is a single step of a pipeline with a measurement unit (comparator), a pipeline register and a pipeline trigger at the output. The quantum Fourier transform (QFT) is part of many quantum algorithms, in particular the Shor'sfactorization algorithm. The structures of digital quantum gates, digital qubits, and a digital quantumcoprocessor capable of performing the QFT are presented. The results of the QFT of a multi-qubit digital quantum coprocessor implemented on one FPGA are presented. For this, a IP core generator of multi-qubit quantum coprocessors was created, cores work was simulated. Models were implemented in FPGAs and their time and hardware characteristics were determined. The execution time of one quantum Fourier transform does not depend on the number of qubits in the digital quantum coprocessor and is commensurate with the time of change of the electron spin. The hardware complexity linearly depends on the number of qubits. With an increase in the number of qubits, the rate of true results of QFT decreases, at 64 qubits it is 1.5%, the decrease is nonlinear
Incompatibility of classical memory for quantum computing is explained. Efficient storage/modification of quantum or classical data is accomplished by using a quantum random-access memory (QRAM). A QRAM applies the principle of quantum superposition for simultaneously accessing all the data stored in the memory cell to assure the superior performance of quantum algorithms. Data reading and writing in a bucket-brigade QRAM are described and the feasibility of its optical implementation is discussed. Quantum computers are understood through layered architectures, viz., 3-, 4-, and 5-layer architectures. Organization of a superconducting quantum computer is illustrated by considering a generic architecture. The superconducting transmon qubits produced inside a dilution refrigerator are manipulated by sequences of microwave pulses. Electronic systems used for producing the control signals and reading the quantum information are described. Quantum computers have been built by several industry giants. Improved quantum processors are being assembled with continuous advancements and refinements. Future computing is likely to follow a hybrid paradigm in which the quantum computers will work in tandem with classical computers in a seamless, integrated environment. Each type of computing will complement the strengths and weaknesses of its counterpart.
This paper proposes a novel approach to quantum computing hardware that diverges from the traditional Von Neumann architecture. The core argument centers around leveraging quantum entanglement and superposition for inherent parallel computation, addressing limitations inherent in the conventional model. We introduce a heterogeneous quantum computing architecture built upon quantum bits (qubits) and quantum circuits, designed to facilitate data processing and control through orchestrated quantum operations. The fundamental innovation lies in moving away from the sequential processing paradigm dictated by Von Neumann architecture, offering a potentially more efficient hardware platform for quantum computations. This architecture aims to unlock significant computational speedups by exploiting the quantum mechanical properties of superposition and entanglement, moving beyond the constraints of classical bit manipulation. The design incorporates a novel control system and qubit connectivity model to maximize computational parallelism. This research contributes to the exploration of alternative hardware designs critical for the advancement of scalable and performant quantum computing systems.
The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures. The resulting architectures overcome the primary challenges of reliability and scalability at the cost of physically unacceptable system area. We find that by exploiting the natural serialization at both the application and the physical microarchitecture level of a quantum computer, we can reduce the area requirement while improving performance. In particular we present a scalable quantum architecture design that employs specialization of the system into memory and computational regions, each individually optimized to match hardware support to the available parallelism. Through careful application and system analysis, we find that our new architecture can yield up to a factor of thirteen savings in area due to specialization. In addition, by providing a memory hierarchy design for quantum computers, we can increase time performance by a factor of eight. This result brings us closer to the realization of a quantum processor that can solve meaningful problems