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Quantum Science and Technology

Multilayered logical qubits and synthesized quantum bits

Ki‐Sung Jin, Gyu‐Il Cha

Published Apr 20, 2023• 6 citations
Publisher

Abstract

Abstract Quantum error correction is likely to be key in obtaining near term quantum advantage. We propose a novel method for providing multiple logical qubits in the correction of quantum errors using classical computers. The core idea of our work is built upon two main pillars: dividing the Hilbert space into reduced Hilbert spaces with individual logical qubits and synthesizing the reduced Hilbert spaces through a mathematical collaborating between classical bits and logical quantum states. We demonstrate that our method supports at least 20 logical qubits in a surface code with a code distance of 3. Furthermore, we generate entangled states of multiple logical qubits from lattice surgery-based surface codes using only physical qubit operations. This approach enables classical computers to support a larger number of logical qubits using less memory and perform faster simulations.

DOI
10.1088/2058-9565/accec5

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Abstract Quantum error correction is likely to be key in obtaining near term quantum advantage. We propose a novel method for providing multiple logical qubits in the correction of quantum errors using classical computers. The core idea of our work is built upon two main pillars: dividing the Hilbert space into reduced Hilbert spaces with individual logical qubits and synthesizing the reduced Hilbert spaces through a mathematical collaborating between classical bits and logical quantum states. We demonstrate that our method supports at least 20 logical qubits in a surface code with a code distance of 3. Furthermore, we generate entangled states of multiple logical qubits from lattice surgery-based surface codes using only physical qubit operations. This approach enables classical computers to support a larger number of logical qubits using less memory and perform faster simulations.
Low-overhead quantum error-correction schemes are essential for enabling quantum computation on registers containing multiple logical qubits. For planar architectures with limited nearest-neighbor qubit connectivity, the surface code has emerged as the leading paradigm. Recent theoretical and experimental work has shown that a physical-qubit connectivity of degree three is sufficient to implement fault-tolerant quantum error correction. In this work, we study lattice surgery in the context of such trivalent architectures and introduce scalable circuit constructions to implement it. Compared with the four-valent measurement scheme, the trivalent lattice-surgery protocol reduces the required resources by O(d)\mathcal{O}(d)O(d) qubits out of a total qubit count of O(d2)\mathcal{O}(d^2)O(d2) and by O(d)\mathcal{O}(d)O(d) two-qubit gates out of a total two-qubit gate count of O(d3)\mathcal{O}(d^3)O(d3). We benchmark the logical fidelity of both lattice-surgery schemes in terms of experimentally realistic simulations targeting an implementation with a fluxonium qubit based architecture and find a potential improvement of up to ≈25%\approx25\%≈25% for distance-three. These results open a way for scalable planar trivalent qubit architectures to host a surface-code-based logical quantum processor.
Quantum computation holds the promise of solving certain complex problems exponentially faster than classical computers. However, the high prevalent noise in current quantum devices impedes the accurate execution of even basic algorithms. This can be remedied by protecting quantum information with a quantum error-correcting code, where the logical information of an algorithmic qubit is spread across multiple physical qubits. Individual quantum errors are then located and corrected by the fault-tolerant measurement of multi-qubit stabilizer operators (parity checks). Unfortunately, error correction and fault tolerance both impose large demands on the qubit overhead: hundreds to thousands of physical qubits per logical qubit. We reduce the spacetime cost of fault tolerance by redesigning key building blocks of an error-corrected quantum computer. First, we develop a combinatorial proof with flag fault tolerance that exponentially reduces the extra qubits needed to measure a stabilizer of any size, while tolerating one fault. We leverage these proofs to then design state preparation circuits for the Steane and Golay codes with 100% yield. Next, we improve error correction on a planar layout by showing that a distance-four code encoding six logical qubits protects information as well as the distance-five surface code, using one-tenth as many physical qubits. Finally, we optimize the time overhead of logical gates in surface code quantum computers by protecting measurement results with a classical code, cutting computation time by a factor of two to six. Our hardware-agnostic optimizations of fault tolerance overheads thus suggest new routes to advance the timeline of error-free quantum computing.
Quantum error correction is needed for quantum computers to be capable of executing algorithms using hundreds of logical qubits in a fault-tolerant manner. Recent experiments have progressed towards this by demonstrating sufficiently low error rates for state preservation of a single logical qubit. However, quantum computation algorithms also require that these logical qubits can be entangled and that gate operations can be performed on them. Lattice surgery is a technique that offers a practical approach for implementing such gates, particularly in planar quantum processor layouts. Here we demonstrate lattice surgery between two distance-three repetition-code qubits by splitting a single distance-three surface-code qubit. Using a quantum circuit that is fault-tolerant for bit-flip errors, we achieve an improvement in the value of the decoded ZZ logical two-qubit observable compared with a similar non-encoded circuit. We therefore demonstrate the functional building blocks needed for lattice-surgery operations on larger-distance codes based on superconducting circuits.
Abstract Quantum error correction is needed for quantum computers to be capable of executing algorithms using hundreds of logical qubits in a fault-tolerant manner. Recent experiments have progressed towards this by demonstrating sufficiently low error rates for state preservation of a single logical qubit. However, quantum computation algorithms also require that these logical qubits can be entangled and that gate operations can be performed on them. Lattice surgery is a technique that offers a practical approach for implementing such gates, particularly in planar quantum processor layouts. Here we demonstrate lattice surgery between two distance-three repetition-code qubits by splitting a single distance-three surface-code qubit. Using a quantum circuit that is fault-tolerant for bit-flip errors, we achieve an improvement in the value of the decoded Z Z logical two-qubit observable compared with a similar non-encoded circuit. We therefore demonstrate the functional building blocks needed for lattice-surgery operations on larger-distance codes based on superconducting circuits.
Abstract In quantum computing, the use of Pauli frames through software traces of classical computers improves computation efficiency. In previous studies, error correction and Pauli operation tracking have been performed simultaneously using integrated Pauli frames in the physical layer. In such a complex processing structure, the number of simultaneous operations processed in the physical layer exponentially increases as the distance of the surface code encoding logical qubit increases. This study proposes a Pauli frame management architecture partitioned into two layers for a lattice surgery‐based surface code and describes its structure and operation rules. To evaluate the effectiveness of our method, we generated a random circuit according to the gate ratios constituting the commonly known quantum circuits and compared the generated circuit with the existing Pauli frame and our method. Simulations show a decrease of about 5% over traditional methods. In the case of experiments that only increase the code distance of the logical qubit, it can be seen that the effect of reducing the physical operation through the logical Pauli frame becomes more important.
Quantum bits have technological imperfections. Additionally, the capacity of a component that can be implemented feasibly is limited. Therefore, distributed quantum computation is required to scale up quantum computers. This dissertation presents a new quantum computer architecture which takes into account imperfections, aimed to realize distributed computation by connecting quantum computers each of which consists of multiple quantum CPUs and memories. Quantum CPUs employ a quantum error correcting code which has faster logical gates and quantum memories employ a code which is superior in space resource requirements. This dissertation focuses on quantum error correcting codes, giving a practical, concrete method for tolerating static losses such as faulty devices for the surface code. Numerical simulation with practical assumptions showed that a yield of functional qubits of 90% is marginally capable of building large-scale systems, by culling the poorer 50% of lattices during post-fabrication testing. Yield 80% is not usable even when culling 90% of generated lattices. For internal connections in a quantum computer and for connections between quantum computers, this dissertation gives a fault-tolerant method that bridges heterogeneous quantum error correcting codes. Numerical simulation showed that the scheme, which discards any quantum state in which any error is detected, always achieves an adequate logical error rate regardless of physical error rates in exchange for increased resource consumption. This dissertation gives a new extension of the surface code suitable for memories. This code is shown to require fewer physical qubits to encode a logical qubit than conventional codes. This code achieves the reduction of 50% physical qubits per a logical qubit. Collectively, the elements to propose the distributed quantum computer architecture are brought together.